Analysis & Synthesis report for DE2_Default
Tue Nov 07 15:49:25 2006
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. Analysis & Synthesis DSP Block Usage Summary
  9. State Machine - |DE2_Default|I2C_AV_Config:u3|mSetup_ST
 10. General Register Statistics
 11. Inverted Register Statistics
 12. Multiplexer Restructuring Statistics (Restructuring Performed)
 13. Source assignments for sld_signaltap:auto_signaltap_0
 14. Source assignments for sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5oi2:auto_generated
 15. Source assignments for sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr
 16. Source assignments for sld_hub:sld_hub_inst
 17. Source assignments for sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine
 18. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 19. Parameter Settings for User Entity Instance: VGA_Audio_PLL:p1|altpll:altpll_component
 20. Parameter Settings for User Entity Instance: I2C_AV_Config:u3
 21. Parameter Settings for User Entity Instance: AUDIO_DAC_ADC:u4
 22. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 23. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 24. Parameter Settings for Inferred Entity Instance: signed_mult:v_22|lpm_mult:Mult0
 25. Parameter Settings for Inferred Entity Instance: signed_mult:v_23|lpm_mult:Mult0
 26. Parameter Settings for Inferred Entity Instance: signed_mult:v_12|lpm_mult:Mult0
 27. Parameter Settings for Inferred Entity Instance: signed_mult:v_13|lpm_mult:Mult0
 28. lpm_mult Parameter Settings by Entity Instance
 29. SignalTap II Logic Analyzer Settings
 30. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                      ;
+------------------------------------+----------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue Nov 07 15:49:25 2006        ;
; Quartus II Version                 ; 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition ;
; Revision Name                      ; DE2_Default                                  ;
; Top-level Entity Name              ; DE2_Default                                  ;
; Family                             ; Cyclone II                                   ;
; Total logic elements               ; 695                                          ;
; Total registers                    ; 453                                          ;
; Total pins                         ; 429                                          ;
; Total virtual pins                 ; 0                                            ;
; Total memory bits                  ; 512                                          ;
; Embedded Multiplier 9-bit elements ; 8                                            ;
; Total PLLs                         ; 1                                            ;
+------------------------------------+----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP2C35F672C6       ;                    ;
; Top-level entity name                                              ; DE2_Default        ; DE2_Default        ;
; Family name                                                        ; Cyclone II         ; Stratix            ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; Maximum DSP Block Usage                                            ; Unlimited          ; Unlimited          ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Cyclone II                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Remove Duplicate Logic                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M4K Memory Blocks                                ; Unlimited          ; Unlimited          ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                     ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                           ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------+
; DE2_Default.v                    ; yes             ; User Verilog HDL File        ; C:/DE2/AnalogSim/DE2_Default.v                                         ;
; I2C_AV_Config.v                  ; yes             ; User Verilog HDL File        ; C:/DE2/AnalogSim/I2C_AV_Config.v                                       ;
; I2C_Controller.v                 ; yes             ; User Verilog HDL File        ; C:/DE2/AnalogSim/I2C_Controller.v                                      ;
; Reset_Delay.v                    ; yes             ; User Verilog HDL File        ; C:/DE2/AnalogSim/Reset_Delay.v                                         ;
; VGA_Audio_PLL.v                  ; yes             ; User Verilog HDL File        ; C:/DE2/AnalogSim/VGA_Audio_PLL.v                                       ;
; AUDIO_DAC_ADC.v                  ; yes             ; User Verilog HDL File        ; C:/DE2/AnalogSim/AUDIO_DAC_ADC.v                                       ;
; altpll.tdf                       ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/altpll.tdf                 ;
; aglobal60.inc                    ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/aglobal60.inc              ;
; stratix_pll.inc                  ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/stratix_pll.inc            ;
; stratixii_pll.inc                ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/stratixii_pll.inc          ;
; cycloneii_pll.inc                ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/cycloneii_pll.inc          ;
; sld_signaltap.vhd                ; yes             ; Encrypted Megafunction       ; c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd          ;
; sld_ela_control.vhd              ; yes             ; Encrypted Megafunction       ; c:/altera/quartus60/libraries/megafunctions/sld_ela_control.vhd        ;
; lpm_shiftreg.tdf                 ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf           ;
; lpm_constant.inc                 ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/lpm_constant.inc           ;
; dffeea.inc                       ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/dffeea.inc                 ;
; sld_mbpmg.vhd                    ; yes             ; Encrypted Megafunction       ; c:/altera/quartus60/libraries/megafunctions/sld_mbpmg.vhd              ;
; lpm_counter.tdf                  ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf            ;
; lpm_decode.inc                   ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/lpm_decode.inc             ;
; lpm_add_sub.inc                  ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.inc            ;
; cmpconst.inc                     ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/cmpconst.inc               ;
; lpm_compare.inc                  ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/lpm_compare.inc            ;
; lpm_counter.inc                  ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/lpm_counter.inc            ;
; alt_synch_counter.inc            ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/alt_synch_counter.inc      ;
; alt_synch_counter_f.inc          ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/alt_synch_counter_f.inc    ;
; alt_counter_f10ke.inc            ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.inc      ;
; alt_counter_stratix.inc          ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/alt_counter_stratix.inc    ;
; db/cntr_mhg.tdf                  ; yes             ; Auto-Generated Megafunction  ; C:/DE2/AnalogSim/db/cntr_mhg.tdf                                       ;
; db/cntr_lqf.tdf                  ; yes             ; Auto-Generated Megafunction  ; C:/DE2/AnalogSim/db/cntr_lqf.tdf                                       ;
; lpm_compare.tdf                  ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/lpm_compare.tdf            ;
; comptree.inc                     ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/comptree.inc               ;
; altshift.inc                     ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/altshift.inc               ;
; db/cmpr_nth.tdf                  ; yes             ; Auto-Generated Megafunction  ; C:/DE2/AnalogSim/db/cmpr_nth.tdf                                       ;
; sld_acquisition_buffer.vhd       ; yes             ; Encrypted Megafunction       ; c:/altera/quartus60/libraries/megafunctions/sld_acquisition_buffer.vhd ;
; db/cntr_blh.tdf                  ; yes             ; Auto-Generated Megafunction  ; C:/DE2/AnalogSim/db/cntr_blh.tdf                                       ;
; lpm_ff.tdf                       ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/lpm_ff.tdf                 ;
; altsyncram.tdf                   ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf             ;
; stratix_ram_block.inc            ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/stratix_ram_block.inc      ;
; lpm_mux.inc                      ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/lpm_mux.inc                ;
; altsyncram.inc                   ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/altsyncram.inc             ;
; a_rdenreg.inc                    ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/a_rdenreg.inc              ;
; altrom.inc                       ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/altrom.inc                 ;
; altram.inc                       ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/altram.inc                 ;
; altdpram.inc                     ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/altdpram.inc               ;
; altqpram.inc                     ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/altqpram.inc               ;
; db/altsyncram_5oi2.tdf           ; yes             ; Auto-Generated Megafunction  ; C:/DE2/AnalogSim/db/altsyncram_5oi2.tdf                                ;
; db/cntr_9ne.tdf                  ; yes             ; Auto-Generated Megafunction  ; C:/DE2/AnalogSim/db/cntr_9ne.tdf                                       ;
; db/cntr_1ff.tdf                  ; yes             ; Auto-Generated Megafunction  ; C:/DE2/AnalogSim/db/cntr_1ff.tdf                                       ;
; sld_rom_sr.vhd                   ; yes             ; Encrypted Megafunction       ; c:/altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd             ;
; sld_hub.vhd                      ; yes             ; Encrypted Megafunction       ; c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd                ;
; lpm_decode.tdf                   ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/lpm_decode.tdf             ;
; declut.inc                       ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/declut.inc                 ;
; db/decode_aoi.tdf                ; yes             ; Auto-Generated Megafunction  ; C:/DE2/AnalogSim/db/decode_aoi.tdf                                     ;
; sld_dffex.vhd                    ; yes             ; Encrypted Megafunction       ; c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd              ;
; lpm_mult.tdf                     ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/lpm_mult.tdf               ;
; multcore.inc                     ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/multcore.inc               ;
; bypassff.inc                     ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/bypassff.inc               ;
; db/mult_co01.tdf                 ; yes             ; Auto-Generated Megafunction  ; C:/DE2/AnalogSim/db/mult_co01.tdf                                      ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------+


+--------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary            ;
+---------------------------------------------+----------+
; Resource                                    ; Usage    ;
+---------------------------------------------+----------+
; Estimated Total logic elements              ; 695      ;
; Total combinational functions               ; 695      ;
; Logic element usage by number of LUT inputs ;          ;
;     -- 4 input functions                    ; 224      ;
;     -- 3 input functions                    ; 319      ;
;     -- <=2 input functions                  ; 152      ;
;         -- Combinational cells for routing  ; 0        ;
; Logic elements by mode                      ;          ;
;     -- normal mode                          ; 391      ;
;     -- arithmetic mode                      ; 304      ;
; Total registers                             ; 453      ;
; I/O pins                                    ; 429      ;
; Total memory bits                           ; 512      ;
; Embedded Multiplier 9-bit elements          ; 8        ;
; Total PLLs                                  ; 1        ;
; Maximum fan-out node                        ; CLOCK_50 ;
; Maximum fan-out                             ; 193      ;
; Total fan-out                               ; 3811     ;
; Average fan-out                             ; 2.40     ;
+---------------------------------------------+----------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+---------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node                                                                        ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                                                                                 ;
+---------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |DE2_Default                                                                                      ; 695 (242)         ; 453 (93)     ; 512         ; 0    ; 8            ; 0       ; 4         ; 429  ; 0            ; |DE2_Default                                                                                                                                                                                                                                                        ;
;    |AUDIO_DAC_ADC:u4|                                                                             ; 125 (125)         ; 82 (82)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|AUDIO_DAC_ADC:u4                                                                                                                                                                                                                                       ;
;    |I2C_AV_Config:u3|                                                                             ; 92 (48)           ; 61 (38)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|I2C_AV_Config:u3                                                                                                                                                                                                                                       ;
;       |I2C_Controller:u0|                                                                         ; 44 (44)           ; 23 (23)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|I2C_AV_Config:u3|I2C_Controller:u0                                                                                                                                                                                                                     ;
;    |Reset_Delay:r0|                                                                               ; 28 (28)           ; 21 (21)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|Reset_Delay:r0                                                                                                                                                                                                                                         ;
;    |VGA_Audio_PLL:p1|                                                                             ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|VGA_Audio_PLL:p1                                                                                                                                                                                                                                       ;
;       |altpll:altpll_component|                                                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|VGA_Audio_PLL:p1|altpll:altpll_component                                                                                                                                                                                                               ;
;    |signed_mult:v_12|                                                                             ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_Default|signed_mult:v_12                                                                                                                                                                                                                                       ;
;       |lpm_mult:Mult0|                                                                            ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_Default|signed_mult:v_12|lpm_mult:Mult0                                                                                                                                                                                                                        ;
;          |mult_co01:auto_generated|                                                               ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_Default|signed_mult:v_12|lpm_mult:Mult0|mult_co01:auto_generated                                                                                                                                                                                               ;
;    |signed_mult:v_13|                                                                             ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_Default|signed_mult:v_13                                                                                                                                                                                                                                       ;
;       |lpm_mult:Mult0|                                                                            ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_Default|signed_mult:v_13|lpm_mult:Mult0                                                                                                                                                                                                                        ;
;          |mult_co01:auto_generated|                                                               ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_Default|signed_mult:v_13|lpm_mult:Mult0|mult_co01:auto_generated                                                                                                                                                                                               ;
;    |signed_mult:v_22|                                                                             ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_Default|signed_mult:v_22                                                                                                                                                                                                                                       ;
;       |lpm_mult:Mult0|                                                                            ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_Default|signed_mult:v_22|lpm_mult:Mult0                                                                                                                                                                                                                        ;
;          |mult_co01:auto_generated|                                                               ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_Default|signed_mult:v_22|lpm_mult:Mult0|mult_co01:auto_generated                                                                                                                                                                                               ;
;    |signed_mult:v_23|                                                                             ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_Default|signed_mult:v_23                                                                                                                                                                                                                                       ;
;       |lpm_mult:Mult0|                                                                            ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_Default|signed_mult:v_23|lpm_mult:Mult0                                                                                                                                                                                                                        ;
;          |mult_co01:auto_generated|                                                               ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_Default|signed_mult:v_23|lpm_mult:Mult0|mult_co01:auto_generated                                                                                                                                                                                               ;
;    |sld_hub:sld_hub_inst|                                                                         ; 96 (44)           ; 73 (7)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_hub:sld_hub_inst                                                                                                                                                                                                                                   ;
;       |lpm_decode:instruction_decoder|                                                            ; 5 (0)             ; 5 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder                                                                                                                                                                                                    ;
;          |decode_aoi:auto_generated|                                                              ; 5 (5)             ; 5 (5)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated                                                                                                                                                                          ;
;       |lpm_shiftreg:jtag_ir_register|                                                             ; 0 (0)             ; 10 (10)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register                                                                                                                                                                                                     ;
;       |sld_dffex:BROADCAST|                                                                       ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_hub:sld_hub_inst|sld_dffex:BROADCAST                                                                                                                                                                                                               ;
;       |sld_dffex:IRF_ENA_0|                                                                       ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0                                                                                                                                                                                                               ;
;       |sld_dffex:IRF_ENA|                                                                         ; 0 (0)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA                                                                                                                                                                                                                 ;
;       |sld_dffex:IRSR|                                                                            ; 4 (4)             ; 9 (9)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_hub:sld_hub_inst|sld_dffex:IRSR                                                                                                                                                                                                                    ;
;       |sld_dffex:RESET|                                                                           ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_hub:sld_hub_inst|sld_dffex:RESET                                                                                                                                                                                                                   ;
;       |sld_dffex:\GEN_IRF:1:IRF|                                                                  ; 0 (0)             ; 5 (5)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF                                                                                                                                                                                                          ;
;       |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|                                                         ; 0 (0)             ; 5 (5)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF                                                                                                                                                                                                 ;
;       |sld_jtag_state_machine:jtag_state_machine|                                                 ; 19 (19)           ; 19 (19)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine                                                                                                                                                                                         ;
;       |sld_rom_sr:HUB_INFO_REG|                                                                   ; 21 (21)           ; 9 (9)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG                                                                                                                                                                                                           ;
;    |sld_signaltap:auto_signaltap_0|                                                               ; 112 (6)           ; 123 (12)     ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0                                                                                                                                                                                                                         ;
;       |altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|                                           ; 0 (0)             ; 0 (0)        ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram                                                                                                                                                                         ;
;          |altsyncram_5oi2:auto_generated|                                                         ; 0 (0)             ; 0 (0)        ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5oi2:auto_generated                                                                                                                                          ;
;       |sld_acquisition_buffer:sld_acquisition_buffer_inst|                                        ; 11 (3)            ; 15 (1)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst                                                                                                                                                                      ;
;          |lpm_counter:\write_address_non_zero_gen:write_pointer_counter|                          ; 8 (0)             ; 7 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter                                                                                                        ;
;             |cntr_blh:auto_generated|                                                             ; 8 (8)             ; 7 (7)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated                                                                                ;
;          |lpm_ff:\gen_non_zero_sample_depth:trigger_address_register|                             ; 0 (0)             ; 7 (7)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_ff:\gen_non_zero_sample_depth:trigger_address_register                                                                                                           ;
;       |sld_ela_control:ela_control|                                                               ; 46 (5)            ; 60 (1)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control                                                                                                                                                                                             ;
;          |lpm_shiftreg:trigger_config_deserialize|                                                ; 0 (0)             ; 16 (16)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize                                                                                                                                                     ;
;          |sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm| ; 8 (0)             ; 20 (0)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm                                                                                                      ;
;             |lpm_shiftreg:trigger_condition_deserialize|                                          ; 0 (0)             ; 12 (12)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize                                                           ;
;             |sld_mbpmg:\trigger_modules_gen:0:trigger_match|                                      ; 8 (0)             ; 8 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match                                                       ;
;                |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1 ;
;                |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1 ;
;                |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1 ;
;                |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1 ;
;          |sld_ela_level_seq_mgr:ela_level_seq_mgr|                                                ; 5 (5)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr                                                                                                                                                     ;
;          |sld_ela_post_trigger_counter:\gen_non_zero_sample_depth:tc1|                            ; 8 (1)             ; 7 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_post_trigger_counter:\gen_non_zero_sample_depth:tc1                                                                                                                                 ;
;             |lpm_counter:post_trigger_counter|                                                    ; 7 (0)             ; 7 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_post_trigger_counter:\gen_non_zero_sample_depth:tc1|lpm_counter:post_trigger_counter                                                                                                ;
;                |cntr_mhg:auto_generated|                                                          ; 7 (7)             ; 7 (7)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_post_trigger_counter:\gen_non_zero_sample_depth:tc1|lpm_counter:post_trigger_counter|cntr_mhg:auto_generated                                                                        ;
;          |sld_ela_seg_state_machine:sm2|                                                          ; 2 (2)             ; 3 (3)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2                                                                                                                                                               ;
;          |sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|                         ; 14 (1)            ; 8 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr                                                                                                                              ;
;             |lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|                         ; 5 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare                                                                  ;
;                |cmpr_nth:auto_generated|                                                          ; 5 (5)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|cmpr_nth:auto_generated                                          ;
;             |lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|                         ; 8 (0)             ; 7 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter                                                                  ;
;                |cntr_lqf:auto_generated|                                                          ; 8 (8)             ; 7 (7)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated                                          ;
;          |sld_ela_state_machine:sm1|                                                              ; 4 (4)             ; 3 (3)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_state_machine:sm1                                                                                                                                                                   ;
;       |sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|          ; 33 (5)            ; 28 (0)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst                                                                                                                                        ;
;          |lpm_counter:\adv_point_3_and_more:advance_pointer_counter|                              ; 2 (0)             ; 2 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter                                                                              ;
;             |cntr_9ne:auto_generated|                                                             ; 2 (2)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_9ne:auto_generated                                                      ;
;          |lpm_counter:read_pointer_counter|                                                       ; 7 (0)             ; 7 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter                                                                                                       ;
;             |cntr_1ff:auto_generated|                                                             ; 7 (7)             ; 7 (7)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_1ff:auto_generated                                                                               ;
;          |lpm_shiftreg:info_data_shift_out|                                                       ; 15 (15)           ; 15 (15)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out                                                                                                       ;
;          |lpm_shiftreg:ram_data_shift_out|                                                        ; 4 (4)             ; 4 (4)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out                                                                                                        ;
;       |sld_rom_sr:crc_rom_sr|                                                                     ; 16 (16)           ; 8 (8)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr                                                                                                                                                                                                   ;
+---------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                             ;
+--------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name                                                                                                                     ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF  ;
+--------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5oi2:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 128          ; 4            ; 128          ; 4            ; 512  ; None ;
+--------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+


+-----------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary        ;
+---------------------------------------+-------------+
; Statistic                             ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit)            ; 0           ;
; Simple Multipliers (18-bit)           ; 4           ;
; Embedded Multiplier Blocks            ; --          ;
; Embedded Multiplier 9-bit elements    ; 8           ;
; Signed Embedded Multipliers           ; 4           ;
; Unsigned Embedded Multipliers         ; 0           ;
; Mixed Sign Embedded Multipliers       ; 0           ;
; Variable Sign Embedded Multipliers    ; 0           ;
; Dedicated Input Shift Register Chains ; 0           ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.


+-------------------------------------------------------------------+
; State Machine - |DE2_Default|I2C_AV_Config:u3|mSetup_ST           ;
+----------------+----------------+----------------+----------------+
; Name           ; mSetup_ST.0000 ; mSetup_ST.0010 ; mSetup_ST.0001 ;
+----------------+----------------+----------------+----------------+
; mSetup_ST.0000 ; 0              ; 0              ; 0              ;
; mSetup_ST.0001 ; 1              ; 0              ; 1              ;
; mSetup_ST.0010 ; 1              ; 1              ; 0              ;
+----------------+----------------+----------------+----------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 453   ;
; Number of registers using Synchronous Clear  ; 39    ;
; Number of registers using Synchronous Load   ; 85    ;
; Number of registers using Asynchronous Clear ; 193   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 255   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------+
; Inverted Register Statistics                               ;
+--------------------------------------------------+---------+
; Inverted Register                                ; Fan out ;
+--------------------------------------------------+---------+
; I2C_AV_Config:u3|I2C_Controller:u0|SD_COUNTER[0] ; 17      ;
; I2C_AV_Config:u3|I2C_Controller:u0|SD_COUNTER[2] ; 17      ;
; I2C_AV_Config:u3|I2C_Controller:u0|SD_COUNTER[3] ; 19      ;
; I2C_AV_Config:u3|I2C_Controller:u0|SD_COUNTER[1] ; 13      ;
; I2C_AV_Config:u3|I2C_Controller:u0|SD_COUNTER[4] ; 11      ;
; I2C_AV_Config:u3|I2C_Controller:u0|SD_COUNTER[5] ; 12      ;
; I2C_AV_Config:u3|I2C_Controller:u0|SCLK          ; 2       ;
; sld_hub:sld_hub_inst|hub_tdo                     ; 2       ;
; I2C_AV_Config:u3|I2C_Controller:u0|END           ; 5       ;
; I2C_AV_Config:u3|I2C_Controller:u0|SDO           ; 4       ;
; Total number of inverted registers = 10          ;         ;
+--------------------------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------+
; 3:1                ; 36 bits   ; 72 LEs        ; 36 LEs               ; 36 LEs                 ; Yes        ; |DE2_Default|v1[12]                                                               ;
; 3:1                ; 36 bits   ; 72 LEs        ; 36 LEs               ; 36 LEs                 ; Yes        ; |DE2_Default|w1[15]                                                               ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |DE2_Default|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5]                             ;
; 5:1                ; 5 bits    ; 15 LEs        ; 5 LEs                ; 10 LEs                 ; Yes        ; |DE2_Default|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]         ;
; 20:1               ; 4 bits    ; 52 LEs        ; 36 LEs               ; 16 LEs                 ; Yes        ; |DE2_Default|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[1]              ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|word_counter[3] ;
; 12:1               ; 4 bits    ; 32 LEs        ; 28 LEs               ; 4 LEs                  ; Yes        ; |DE2_Default|sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0]      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------+


+-------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0 ;
+---------------------------------+-------+------+------+
; Assignment                      ; Value ; From ; To   ;
+---------------------------------+-------+------+------+
; NOT_GATE_PUSH_BACK              ; OFF   ; -    ; -    ;
; POWER_UP_LEVEL                  ; LOW   ; -    ; -    ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -    ;
+---------------------------------+-------+------+------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5oi2:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                     ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                      ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------+


+-----------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr ;
+----------------------+-------+------+---------------------------------------+
; Assignment           ; Value ; From ; To                                    ;
+----------------------+-------+------+---------------------------------------+
; AUTO_ROM_RECOGNITION ; OFF   ; -    ; -                                     ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[0]                       ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[1]                       ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[2]                       ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[3]                       ;
+----------------------+-------+------+---------------------------------------+


+----------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst              ;
+------------------------------+-------+------+------------+
; Assignment                   ; Value ; From ; To         ;
+------------------------------+-------+------+------------+
; IGNORE_LCELL_BUFFERS         ; OFF   ; -    ; -          ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF   ; -    ; -          ;
; NOT_GATE_PUSH_BACK           ; OFF   ; -    ; CLR_SIGNAL ;
; POWER_UP_LEVEL               ; LOW   ; -    ; CLR_SIGNAL ;
+------------------------------+-------+------+------------+


+---------------------------------------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine ;
+----------------+-------+------+-------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                    ;
+----------------+-------+------+-------------------------------------------------------+
; POWER_UP_LEVEL ; Low   ; -    ; state[0]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[1]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[2]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[3]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[4]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[5]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[6]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[7]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[8]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[9]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[10]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[11]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[12]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[13]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[14]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[15]                                             ;
+----------------+-------+------+-------------------------------------------------------+


+---------------------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG ;
+----------------------+-------+------+-------------------------------+
; Assignment           ; Value ; From ; To                            ;
+----------------------+-------+------+-------------------------------+
; AUTO_ROM_RECOGNITION ; OFF   ; -    ; -                             ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[0]               ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[1]               ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[2]               ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[3]               ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[4]               ;
+----------------------+-------+------+-------------------------------+


+---------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: VGA_Audio_PLL:p1|altpll:altpll_component ;
+-------------------------------+-------------------+-----------------------------------+
; Parameter Name                ; Value             ; Type                              ;
+-------------------------------+-------------------+-----------------------------------+
; OPERATION_MODE                ; NORMAL            ; Untyped                           ;
; PLL_TYPE                      ; FAST              ; Untyped                           ;
; QUALIFY_CONF_DONE             ; OFF               ; Untyped                           ;
; COMPENSATE_CLOCK              ; CLK0              ; Untyped                           ;
; SCAN_CHAIN                    ; LONG              ; Untyped                           ;
; PRIMARY_CLOCK                 ; INCLK0            ; Untyped                           ;
; INCLK0_INPUT_FREQUENCY        ; 37037             ; Integer                           ;
; INCLK1_INPUT_FREQUENCY        ; 0                 ; Untyped                           ;
; GATE_LOCK_SIGNAL              ; NO                ; Untyped                           ;
; GATE_LOCK_COUNTER             ; 0                 ; Untyped                           ;
; LOCK_HIGH                     ; 1                 ; Untyped                           ;
; LOCK_LOW                      ; 1                 ; Untyped                           ;
; VALID_LOCK_MULTIPLIER         ; 1                 ; Untyped                           ;
; INVALID_LOCK_MULTIPLIER       ; 5                 ; Untyped                           ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF               ; Untyped                           ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF               ; Untyped                           ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF               ; Untyped                           ;
; SKIP_VCO                      ; OFF               ; Untyped                           ;
; SWITCH_OVER_COUNTER           ; 0                 ; Untyped                           ;
; SWITCH_OVER_TYPE              ; AUTO              ; Untyped                           ;
; FEEDBACK_SOURCE               ; EXTCLK0           ; Untyped                           ;
; BANDWIDTH                     ; 0                 ; Untyped                           ;
; BANDWIDTH_TYPE                ; AUTO              ; Untyped                           ;
; SPREAD_FREQUENCY              ; 0                 ; Untyped                           ;
; DOWN_SPREAD                   ; 0                 ; Untyped                           ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF               ; Untyped                           ;
; CLK5_MULTIPLY_BY              ; 1                 ; Untyped                           ;
; CLK4_MULTIPLY_BY              ; 1                 ; Untyped                           ;
; CLK3_MULTIPLY_BY              ; 1                 ; Untyped                           ;
; CLK2_MULTIPLY_BY              ; 14                ; Integer                           ;
; CLK1_MULTIPLY_BY              ; 2                 ; Integer                           ;
; CLK0_MULTIPLY_BY              ; 14                ; Integer                           ;
; CLK5_DIVIDE_BY                ; 1                 ; Untyped                           ;
; CLK4_DIVIDE_BY                ; 1                 ; Untyped                           ;
; CLK3_DIVIDE_BY                ; 1                 ; Untyped                           ;
; CLK2_DIVIDE_BY                ; 15                ; Integer                           ;
; CLK1_DIVIDE_BY                ; 3                 ; Integer                           ;
; CLK0_DIVIDE_BY                ; 15                ; Integer                           ;
; CLK5_PHASE_SHIFT              ; 0                 ; Untyped                           ;
; CLK4_PHASE_SHIFT              ; 0                 ; Untyped                           ;
; CLK3_PHASE_SHIFT              ; 0                 ; Untyped                           ;
; CLK2_PHASE_SHIFT              ; -9921             ; Untyped                           ;
; CLK1_PHASE_SHIFT              ; 0                 ; Untyped                           ;
; CLK0_PHASE_SHIFT              ; 0                 ; Untyped                           ;
; CLK5_TIME_DELAY               ; 0                 ; Untyped                           ;
; CLK4_TIME_DELAY               ; 0                 ; Untyped                           ;
; CLK3_TIME_DELAY               ; 0                 ; Untyped                           ;
; CLK2_TIME_DELAY               ; 0                 ; Untyped                           ;
; CLK1_TIME_DELAY               ; 0                 ; Untyped                           ;
; CLK0_TIME_DELAY               ; 0                 ; Untyped                           ;
; CLK5_DUTY_CYCLE               ; 50                ; Untyped                           ;
; CLK4_DUTY_CYCLE               ; 50                ; Untyped                           ;
; CLK3_DUTY_CYCLE               ; 50                ; Untyped                           ;
; CLK2_DUTY_CYCLE               ; 50                ; Integer                           ;
; CLK1_DUTY_CYCLE               ; 50                ; Integer                           ;
; CLK0_DUTY_CYCLE               ; 50                ; Integer                           ;
; EXTCLK3_MULTIPLY_BY           ; 1                 ; Untyped                           ;
; EXTCLK2_MULTIPLY_BY           ; 1                 ; Untyped                           ;
; EXTCLK1_MULTIPLY_BY           ; 1                 ; Untyped                           ;
; EXTCLK0_MULTIPLY_BY           ; 1                 ; Untyped                           ;
; EXTCLK3_DIVIDE_BY             ; 1                 ; Untyped                           ;
; EXTCLK2_DIVIDE_BY             ; 1                 ; Untyped                           ;
; EXTCLK1_DIVIDE_BY             ; 1                 ; Untyped                           ;
; EXTCLK0_DIVIDE_BY             ; 1                 ; Untyped                           ;
; EXTCLK3_PHASE_SHIFT           ; 0                 ; Untyped                           ;
; EXTCLK2_PHASE_SHIFT           ; 0                 ; Untyped                           ;
; EXTCLK1_PHASE_SHIFT           ; 0                 ; Untyped                           ;
; EXTCLK0_PHASE_SHIFT           ; 0                 ; Untyped                           ;
; EXTCLK3_TIME_DELAY            ; 0                 ; Untyped                           ;
; EXTCLK2_TIME_DELAY            ; 0                 ; Untyped                           ;
; EXTCLK1_TIME_DELAY            ; 0                 ; Untyped                           ;
; EXTCLK0_TIME_DELAY            ; 0                 ; Untyped                           ;
; EXTCLK3_DUTY_CYCLE            ; 50                ; Untyped                           ;
; EXTCLK2_DUTY_CYCLE            ; 50                ; Untyped                           ;
; EXTCLK1_DUTY_CYCLE            ; 50                ; Untyped                           ;
; EXTCLK0_DUTY_CYCLE            ; 50                ; Untyped                           ;
; VCO_MULTIPLY_BY               ; 0                 ; Untyped                           ;
; VCO_DIVIDE_BY                 ; 0                 ; Untyped                           ;
; SCLKOUT0_PHASE_SHIFT          ; 0                 ; Untyped                           ;
; SCLKOUT1_PHASE_SHIFT          ; 0                 ; Untyped                           ;
; VCO_MIN                       ; 0                 ; Untyped                           ;
; VCO_MAX                       ; 0                 ; Untyped                           ;
; VCO_CENTER                    ; 0                 ; Untyped                           ;
; PFD_MIN                       ; 0                 ; Untyped                           ;
; PFD_MAX                       ; 0                 ; Untyped                           ;
; M_INITIAL                     ; 0                 ; Untyped                           ;
; M                             ; 0                 ; Untyped                           ;
; N                             ; 1                 ; Untyped                           ;
; M2                            ; 1                 ; Untyped                           ;
; N2                            ; 1                 ; Untyped                           ;
; SS                            ; 1                 ; Untyped                           ;
; C0_HIGH                       ; 0                 ; Untyped                           ;
; C1_HIGH                       ; 0                 ; Untyped                           ;
; C2_HIGH                       ; 0                 ; Untyped                           ;
; C3_HIGH                       ; 0                 ; Untyped                           ;
; C4_HIGH                       ; 0                 ; Untyped                           ;
; C5_HIGH                       ; 0                 ; Untyped                           ;
; C0_LOW                        ; 0                 ; Untyped                           ;
; C1_LOW                        ; 0                 ; Untyped                           ;
; C2_LOW                        ; 0                 ; Untyped                           ;
; C3_LOW                        ; 0                 ; Untyped                           ;
; C4_LOW                        ; 0                 ; Untyped                           ;
; C5_LOW                        ; 0                 ; Untyped                           ;
; C0_INITIAL                    ; 0                 ; Untyped                           ;
; C1_INITIAL                    ; 0                 ; Untyped                           ;
; C2_INITIAL                    ; 0                 ; Untyped                           ;
; C3_INITIAL                    ; 0                 ; Untyped                           ;
; C4_INITIAL                    ; 0                 ; Untyped                           ;
; C5_INITIAL                    ; 0                 ; Untyped                           ;
; C0_MODE                       ; BYPASS            ; Untyped                           ;
; C1_MODE                       ; BYPASS            ; Untyped                           ;
; C2_MODE                       ; BYPASS            ; Untyped                           ;
; C3_MODE                       ; BYPASS            ; Untyped                           ;
; C4_MODE                       ; BYPASS            ; Untyped                           ;
; C5_MODE                       ; BYPASS            ; Untyped                           ;
; C0_PH                         ; 0                 ; Untyped                           ;
; C1_PH                         ; 0                 ; Untyped                           ;
; C2_PH                         ; 0                 ; Untyped                           ;
; C3_PH                         ; 0                 ; Untyped                           ;
; C4_PH                         ; 0                 ; Untyped                           ;
; C5_PH                         ; 0                 ; Untyped                           ;
; L0_HIGH                       ; 1                 ; Untyped                           ;
; L1_HIGH                       ; 1                 ; Untyped                           ;
; G0_HIGH                       ; 1                 ; Untyped                           ;
; G1_HIGH                       ; 1                 ; Untyped                           ;
; G2_HIGH                       ; 1                 ; Untyped                           ;
; G3_HIGH                       ; 1                 ; Untyped                           ;
; E0_HIGH                       ; 1                 ; Untyped                           ;
; E1_HIGH                       ; 1                 ; Untyped                           ;
; E2_HIGH                       ; 1                 ; Untyped                           ;
; E3_HIGH                       ; 1                 ; Untyped                           ;
; L0_LOW                        ; 1                 ; Untyped                           ;
; L1_LOW                        ; 1                 ; Untyped                           ;
; G0_LOW                        ; 1                 ; Untyped                           ;
; G1_LOW                        ; 1                 ; Untyped                           ;
; G2_LOW                        ; 1                 ; Untyped                           ;
; G3_LOW                        ; 1                 ; Untyped                           ;
; E0_LOW                        ; 1                 ; Untyped                           ;
; E1_LOW                        ; 1                 ; Untyped                           ;
; E2_LOW                        ; 1                 ; Untyped                           ;
; E3_LOW                        ; 1                 ; Untyped                           ;
; L0_INITIAL                    ; 1                 ; Untyped                           ;
; L1_INITIAL                    ; 1                 ; Untyped                           ;
; G0_INITIAL                    ; 1                 ; Untyped                           ;
; G1_INITIAL                    ; 1                 ; Untyped                           ;
; G2_INITIAL                    ; 1                 ; Untyped                           ;
; G3_INITIAL                    ; 1                 ; Untyped                           ;
; E0_INITIAL                    ; 1                 ; Untyped                           ;
; E1_INITIAL                    ; 1                 ; Untyped                           ;
; E2_INITIAL                    ; 1                 ; Untyped                           ;
; E3_INITIAL                    ; 1                 ; Untyped                           ;
; L0_MODE                       ; BYPASS            ; Untyped                           ;
; L1_MODE                       ; BYPASS            ; Untyped                           ;
; G0_MODE                       ; BYPASS            ; Untyped                           ;
; G1_MODE                       ; BYPASS            ; Untyped                           ;
; G2_MODE                       ; BYPASS            ; Untyped                           ;
; G3_MODE                       ; BYPASS            ; Untyped                           ;
; E0_MODE                       ; BYPASS            ; Untyped                           ;
; E1_MODE                       ; BYPASS            ; Untyped                           ;
; E2_MODE                       ; BYPASS            ; Untyped                           ;
; E3_MODE                       ; BYPASS            ; Untyped                           ;
; L0_PH                         ; 0                 ; Untyped                           ;
; L1_PH                         ; 0                 ; Untyped                           ;
; G0_PH                         ; 0                 ; Untyped                           ;
; G1_PH                         ; 0                 ; Untyped                           ;
; G2_PH                         ; 0                 ; Untyped                           ;
; G3_PH                         ; 0                 ; Untyped                           ;
; E0_PH                         ; 0                 ; Untyped                           ;
; E1_PH                         ; 0                 ; Untyped                           ;
; E2_PH                         ; 0                 ; Untyped                           ;
; E3_PH                         ; 0                 ; Untyped                           ;
; M_PH                          ; 0                 ; Untyped                           ;
; C1_USE_CASC_IN                ; 0                 ; Untyped                           ;
; C2_USE_CASC_IN                ; 0                 ; Untyped                           ;
; C3_USE_CASC_IN                ; 0                 ; Untyped                           ;
; C4_USE_CASC_IN                ; 0                 ; Untyped                           ;
; C5_USE_CASC_IN                ; 0                 ; Untyped                           ;
; CLK0_COUNTER                  ; G0                ; Untyped                           ;
; CLK1_COUNTER                  ; G0                ; Untyped                           ;
; CLK2_COUNTER                  ; G0                ; Untyped                           ;
; CLK3_COUNTER                  ; G0                ; Untyped                           ;
; CLK4_COUNTER                  ; G0                ; Untyped                           ;
; CLK5_COUNTER                  ; G0                ; Untyped                           ;
; L0_TIME_DELAY                 ; 0                 ; Untyped                           ;
; L1_TIME_DELAY                 ; 0                 ; Untyped                           ;
; G0_TIME_DELAY                 ; 0                 ; Untyped                           ;
; G1_TIME_DELAY                 ; 0                 ; Untyped                           ;
; G2_TIME_DELAY                 ; 0                 ; Untyped                           ;
; G3_TIME_DELAY                 ; 0                 ; Untyped                           ;
; E0_TIME_DELAY                 ; 0                 ; Untyped                           ;
; E1_TIME_DELAY                 ; 0                 ; Untyped                           ;
; E2_TIME_DELAY                 ; 0                 ; Untyped                           ;
; E3_TIME_DELAY                 ; 0                 ; Untyped                           ;
; M_TIME_DELAY                  ; 0                 ; Untyped                           ;
; N_TIME_DELAY                  ; 0                 ; Untyped                           ;
; EXTCLK3_COUNTER               ; E3                ; Untyped                           ;
; EXTCLK2_COUNTER               ; E2                ; Untyped                           ;
; EXTCLK1_COUNTER               ; E1                ; Untyped                           ;
; EXTCLK0_COUNTER               ; E0                ; Untyped                           ;
; ENABLE0_COUNTER               ; L0                ; Untyped                           ;
; ENABLE1_COUNTER               ; L0                ; Untyped                           ;
; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped                           ;
; LOOP_FILTER_R                 ;  1.000000         ; Untyped                           ;
; LOOP_FILTER_C                 ; 5                 ; Untyped                           ;
; VCO_POST_SCALE                ; 0                 ; Untyped                           ;
; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped                           ;
; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped                           ;
; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped                           ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II        ; Untyped                           ;
; PORT_CLKENA0                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKENA1                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKENA2                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKENA3                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKENA4                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKENA5                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLK0                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLK1                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLK2                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_EXTCLK3                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKBAD0                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKBAD1                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLK0                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLK1                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLK2                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLK3                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLK4                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLK5                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANDATA                 ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANDATAOUT              ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANDONE                 ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_ACTIVECLOCK              ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKLOSS                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_INCLK1                   ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_INCLK0                   ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_FBIN                     ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_PLLENA                   ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_CLKSWITCH                ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_ARESET                   ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_PFDENA                   ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANCLK                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANACLR                 ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANREAD                 ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_SCANWRITE                ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped                           ;
; PORT_LOCKED                   ; PORT_CONNECTIVITY ; Untyped                           ;
; M_TEST_SOURCE                 ; 5                 ; Untyped                           ;
; C0_TEST_SOURCE                ; 5                 ; Untyped                           ;
; C1_TEST_SOURCE                ; 5                 ; Untyped                           ;
; C2_TEST_SOURCE                ; 5                 ; Untyped                           ;
; C3_TEST_SOURCE                ; 5                 ; Untyped                           ;
; C4_TEST_SOURCE                ; 5                 ; Untyped                           ;
; C5_TEST_SOURCE                ; 5                 ; Untyped                           ;
; DEVICE_FAMILY                 ; Cyclone II        ; Untyped                           ;
; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY                        ;
; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                      ;
; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                      ;
; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE                    ;
+-------------------------------+-------------------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------+
; Parameter Settings for User Entity Instance: I2C_AV_Config:u3 ;
+----------------+----------+-----------------------------------+
; Parameter Name ; Value    ; Type                              ;
+----------------+----------+-----------------------------------+
; CLK_Freq       ; 50000000 ; Integer                           ;
; I2C_Freq       ; 20000    ; Integer                           ;
; LUT_SIZE       ; 13       ; Integer                           ;
; Dummy_DATA     ; 0        ; Integer                           ;
; SET_LIN_L      ; 1        ; Integer                           ;
; SET_LIN_R      ; 2        ; Integer                           ;
; SET_HEAD_L     ; 3        ; Integer                           ;
; SET_HEAD_R     ; 4        ; Integer                           ;
; A_PATH_CTRL    ; 5        ; Integer                           ;
; D_PATH_CTRL    ; 6        ; Integer                           ;
; POWER_ON       ; 7        ; Integer                           ;
; SET_FORMAT     ; 8        ; Integer                           ;
; SAMPLE_CTRL    ; 9        ; Integer                           ;
; SET_ACTIVE     ; 10       ; Integer                           ;
; SET_VIDEO      ; 11       ; Integer                           ;
+----------------+----------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------+
; Parameter Settings for User Entity Instance: AUDIO_DAC_ADC:u4 ;
+------------------+----------+---------------------------------+
; Parameter Name   ; Value    ; Type                            ;
+------------------+----------+---------------------------------+
; REF_CLK          ; 18432000 ; Integer                         ;
; SAMPLE_RATE      ; 48000    ; Integer                         ;
; DATA_WIDTH       ; 16       ; Integer                         ;
; CHANNEL_NUM      ; 2        ; Integer                         ;
; SIN_SAMPLE_DATA  ; 48       ; Integer                         ;
; FLASH_DATA_NUM   ; 1048576  ; Integer                         ;
; SDRAM_DATA_NUM   ; 4194304  ; Integer                         ;
; SRAM_DATA_NUM    ; 262144   ; Integer                         ;
; FLASH_ADDR_WIDTH ; 20       ; Integer                         ;
; SDRAM_ADDR_WIDTH ; 22       ; Integer                         ;
; SRAM_ADDR_WIDTH  ; 18       ; Integer                         ;
; FLASH_DATA_WIDTH ; 8        ; Integer                         ;
; SDRAM_DATA_WIDTH ; 16       ; Integer                         ;
; SRAM_DATA_WIDTH  ; 16       ; Integer                         ;
; ADC_loop         ; 0        ; Integer                         ;
; FLASH_DATA       ; 1        ; Integer                         ;
; SDRAM_DATA       ; 2        ; Integer                         ;
; SRAM_DATA        ; 3        ; Integer                         ;
+------------------+----------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0 ;
+-----------------------------+------------------------------+--------------------+
; Parameter Name              ; Value                        ; Type               ;
+-----------------------------+------------------------------+--------------------+
; lpm_type                    ; sld_signaltap                ; String             ;
; sld_node_info               ; 536899072                    ; Untyped            ;
; sld_ip_version              ; 4                            ; Integer            ;
; sld_ip_minor_version        ; 0                            ; Integer            ;
; sld_common_ip_version       ; 0                            ; Integer            ;
; sld_data_bits               ; 4                            ; Untyped            ;
; sld_trigger_bits            ; 4                            ; Untyped            ;
; sld_data_bit_cntr_bits      ; 2                            ; Untyped            ;
; sld_node_crc_bits           ; 32                           ; Integer            ;
; sld_node_crc_hiword         ; 21303                        ; Untyped            ;
; sld_node_crc_loword         ; 33425                        ; Untyped            ;
; sld_incremental_routing     ; 0                            ; Integer            ;
; sld_sample_depth            ; 128                          ; Untyped            ;
; sld_mem_address_bits        ; 7                            ; Untyped            ;
; sld_ram_block_type          ; AUTO                         ; String             ;
; sld_trigger_level           ; 1                            ; Untyped            ;
; sld_trigger_in_enabled      ; 0                            ; Untyped            ;
; sld_advanced_trigger_entity ; basic,1,                     ; Untyped            ;
; sld_trigger_level_pipeline  ; 1                            ; Untyped            ;
; sld_enable_advanced_trigger ; 0                            ; Untyped            ;
; sld_advanced_trigger_1      ; NONE                         ; String             ;
; sld_advanced_trigger_2      ; NONE                         ; String             ;
; sld_advanced_trigger_3      ; NONE                         ; String             ;
; sld_advanced_trigger_4      ; NONE                         ; String             ;
; sld_advanced_trigger_5      ; NONE                         ; String             ;
; sld_advanced_trigger_6      ; NONE                         ; String             ;
; sld_advanced_trigger_7      ; NONE                         ; String             ;
; sld_advanced_trigger_8      ; NONE                         ; String             ;
; sld_advanced_trigger_9      ; NONE                         ; String             ;
; sld_advanced_trigger_10     ; NONE                         ; String             ;
; sld_inversion_mask_length   ; 28                           ; Untyped            ;
; sld_inversion_mask          ; 0000000000000000000000000000 ; Untyped            ;
; sld_power_up_trigger        ; 0                            ; Untyped            ;
+-----------------------------+------------------------------+--------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst ;
+--------------------------+----------------------------------+---------+
; Parameter Name           ; Value                            ; Type    ;
+--------------------------+----------------------------------+---------+
; sld_hub_ip_version       ; 1                                ; Untyped ;
; sld_hub_ip_minor_version ; 3                                ; Untyped ;
; sld_common_ip_version    ; 0                                ; Untyped ;
; device_family            ; Cyclone II                       ; Untyped ;
; n_nodes                  ; 1                                ; Untyped ;
; n_sel_bits               ; 1                                ; Untyped ;
; n_node_ir_bits           ; 8                                ; Untyped ;
; node_info                ; 00100000000000000110111000000000 ; Binary  ;
; compilation_mode         ; 0                                ; Untyped ;
+--------------------------+----------------------------------+---------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: signed_mult:v_22|lpm_mult:Mult0  ;
+------------------------------------------------+------------+---------------------+
; Parameter Name                                 ; Value      ; Type                ;
+------------------------------------------------+------------+---------------------+
; AUTO_CARRY_CHAINS                              ; ON         ; AUTO_CARRY          ;
; IGNORE_CARRY_BUFFERS                           ; OFF        ; IGNORE_CARRY        ;
; AUTO_CASCADE_CHAINS                            ; ON         ; AUTO_CASCADE        ;
; IGNORE_CASCADE_BUFFERS                         ; OFF        ; IGNORE_CASCADE      ;
; LPM_WIDTHA                                     ; 18         ; Untyped             ;
; LPM_WIDTHB                                     ; 17         ; Untyped             ;
; LPM_WIDTHP                                     ; 35         ; Untyped             ;
; LPM_WIDTHR                                     ; 35         ; Untyped             ;
; LPM_WIDTHS                                     ; 1          ; Untyped             ;
; LPM_REPRESENTATION                             ; SIGNED     ; Untyped             ;
; LPM_PIPELINE                                   ; 0          ; Untyped             ;
; LATENCY                                        ; 0          ; Untyped             ;
; INPUT_A_IS_CONSTANT                            ; NO         ; Untyped             ;
; INPUT_B_IS_CONSTANT                            ; NO         ; Untyped             ;
; USE_EAB                                        ; OFF        ; Untyped             ;
; MAXIMIZE_SPEED                                 ; 6          ; Untyped             ;
; DEVICE_FAMILY                                  ; Cyclone II ; Untyped             ;
; CARRY_CHAIN                                    ; MANUAL     ; Untyped             ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT        ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO       ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0          ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0          ; Untyped             ;
; CBXI_PARAMETER                                 ; mult_co01  ; Untyped             ;
; INPUT_A_FIXED_VALUE                            ; Bx         ; Untyped             ;
; INPUT_B_FIXED_VALUE                            ; Bx         ; Untyped             ;
+------------------------------------------------+------------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: signed_mult:v_23|lpm_mult:Mult0  ;
+------------------------------------------------+------------+---------------------+
; Parameter Name                                 ; Value      ; Type                ;
+------------------------------------------------+------------+---------------------+
; AUTO_CARRY_CHAINS                              ; ON         ; AUTO_CARRY          ;
; IGNORE_CARRY_BUFFERS                           ; OFF        ; IGNORE_CARRY        ;
; AUTO_CASCADE_CHAINS                            ; ON         ; AUTO_CASCADE        ;
; IGNORE_CASCADE_BUFFERS                         ; OFF        ; IGNORE_CASCADE      ;
; LPM_WIDTHA                                     ; 18         ; Untyped             ;
; LPM_WIDTHB                                     ; 17         ; Untyped             ;
; LPM_WIDTHP                                     ; 35         ; Untyped             ;
; LPM_WIDTHR                                     ; 35         ; Untyped             ;
; LPM_WIDTHS                                     ; 1          ; Untyped             ;
; LPM_REPRESENTATION                             ; SIGNED     ; Untyped             ;
; LPM_PIPELINE                                   ; 0          ; Untyped             ;
; LATENCY                                        ; 0          ; Untyped             ;
; INPUT_A_IS_CONSTANT                            ; NO         ; Untyped             ;
; INPUT_B_IS_CONSTANT                            ; NO         ; Untyped             ;
; USE_EAB                                        ; OFF        ; Untyped             ;
; MAXIMIZE_SPEED                                 ; 6          ; Untyped             ;
; DEVICE_FAMILY                                  ; Cyclone II ; Untyped             ;
; CARRY_CHAIN                                    ; MANUAL     ; Untyped             ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT        ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO       ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0          ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0          ; Untyped             ;
; CBXI_PARAMETER                                 ; mult_co01  ; Untyped             ;
; INPUT_A_FIXED_VALUE                            ; Bx         ; Untyped             ;
; INPUT_B_FIXED_VALUE                            ; Bx         ; Untyped             ;
+------------------------------------------------+------------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: signed_mult:v_12|lpm_mult:Mult0  ;
+------------------------------------------------+------------+---------------------+
; Parameter Name                                 ; Value      ; Type                ;
+------------------------------------------------+------------+---------------------+
; AUTO_CARRY_CHAINS                              ; ON         ; AUTO_CARRY          ;
; IGNORE_CARRY_BUFFERS                           ; OFF        ; IGNORE_CARRY        ;
; AUTO_CASCADE_CHAINS                            ; ON         ; AUTO_CASCADE        ;
; IGNORE_CASCADE_BUFFERS                         ; OFF        ; IGNORE_CASCADE      ;
; LPM_WIDTHA                                     ; 18         ; Untyped             ;
; LPM_WIDTHB                                     ; 17         ; Untyped             ;
; LPM_WIDTHP                                     ; 35         ; Untyped             ;
; LPM_WIDTHR                                     ; 35         ; Untyped             ;
; LPM_WIDTHS                                     ; 1          ; Untyped             ;
; LPM_REPRESENTATION                             ; SIGNED     ; Untyped             ;
; LPM_PIPELINE                                   ; 0          ; Untyped             ;
; LATENCY                                        ; 0          ; Untyped             ;
; INPUT_A_IS_CONSTANT                            ; NO         ; Untyped             ;
; INPUT_B_IS_CONSTANT                            ; NO         ; Untyped             ;
; USE_EAB                                        ; OFF        ; Untyped             ;
; MAXIMIZE_SPEED                                 ; 6          ; Untyped             ;
; DEVICE_FAMILY                                  ; Cyclone II ; Untyped             ;
; CARRY_CHAIN                                    ; MANUAL     ; Untyped             ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT        ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO       ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0          ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0          ; Untyped             ;
; CBXI_PARAMETER                                 ; mult_co01  ; Untyped             ;
; INPUT_A_FIXED_VALUE                            ; Bx         ; Untyped             ;
; INPUT_B_FIXED_VALUE                            ; Bx         ; Untyped             ;
+------------------------------------------------+------------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: signed_mult:v_13|lpm_mult:Mult0  ;
+------------------------------------------------+------------+---------------------+
; Parameter Name                                 ; Value      ; Type                ;
+------------------------------------------------+------------+---------------------+
; AUTO_CARRY_CHAINS                              ; ON         ; AUTO_CARRY          ;
; IGNORE_CARRY_BUFFERS                           ; OFF        ; IGNORE_CARRY        ;
; AUTO_CASCADE_CHAINS                            ; ON         ; AUTO_CASCADE        ;
; IGNORE_CASCADE_BUFFERS                         ; OFF        ; IGNORE_CASCADE      ;
; LPM_WIDTHA                                     ; 18         ; Untyped             ;
; LPM_WIDTHB                                     ; 17         ; Untyped             ;
; LPM_WIDTHP                                     ; 35         ; Untyped             ;
; LPM_WIDTHR                                     ; 35         ; Untyped             ;
; LPM_WIDTHS                                     ; 1          ; Untyped             ;
; LPM_REPRESENTATION                             ; SIGNED     ; Untyped             ;
; LPM_PIPELINE                                   ; 0          ; Untyped             ;
; LATENCY                                        ; 0          ; Untyped             ;
; INPUT_A_IS_CONSTANT                            ; NO         ; Untyped             ;
; INPUT_B_IS_CONSTANT                            ; NO         ; Untyped             ;
; USE_EAB                                        ; OFF        ; Untyped             ;
; MAXIMIZE_SPEED                                 ; 6          ; Untyped             ;
; DEVICE_FAMILY                                  ; Cyclone II ; Untyped             ;
; CARRY_CHAIN                                    ; MANUAL     ; Untyped             ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT        ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO       ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0          ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0          ; Untyped             ;
; CBXI_PARAMETER                                 ; mult_co01  ; Untyped             ;
; INPUT_A_FIXED_VALUE                            ; Bx         ; Untyped             ;
; INPUT_B_FIXED_VALUE                            ; Bx         ; Untyped             ;
+------------------------------------------------+------------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance                          ;
+---------------------------------------+---------------------------------+
; Name                                  ; Value                           ;
+---------------------------------------+---------------------------------+
; Number of entity instances            ; 4                               ;
; Entity Instance                       ; signed_mult:v_22|lpm_mult:Mult0 ;
;     -- LPM_WIDTHA                     ; 18                              ;
;     -- LPM_WIDTHB                     ; 17                              ;
;     -- LPM_WIDTHP                     ; 35                              ;
;     -- LPM_REPRESENTATION             ; SIGNED                          ;
;     -- INPUT_A_IS_CONSTANT            ; NO                              ;
;     -- INPUT_B_IS_CONSTANT            ; NO                              ;
;     -- USE_EAB                        ; OFF                             ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                            ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                              ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                              ;
; Entity Instance                       ; signed_mult:v_23|lpm_mult:Mult0 ;
;     -- LPM_WIDTHA                     ; 18                              ;
;     -- LPM_WIDTHB                     ; 17                              ;
;     -- LPM_WIDTHP                     ; 35                              ;
;     -- LPM_REPRESENTATION             ; SIGNED                          ;
;     -- INPUT_A_IS_CONSTANT            ; NO                              ;
;     -- INPUT_B_IS_CONSTANT            ; NO                              ;
;     -- USE_EAB                        ; OFF                             ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                            ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                              ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                              ;
; Entity Instance                       ; signed_mult:v_12|lpm_mult:Mult0 ;
;     -- LPM_WIDTHA                     ; 18                              ;
;     -- LPM_WIDTHB                     ; 17                              ;
;     -- LPM_WIDTHP                     ; 35                              ;
;     -- LPM_REPRESENTATION             ; SIGNED                          ;
;     -- INPUT_A_IS_CONSTANT            ; NO                              ;
;     -- INPUT_B_IS_CONSTANT            ; NO                              ;
;     -- USE_EAB                        ; OFF                             ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                            ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                              ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                              ;
; Entity Instance                       ; signed_mult:v_13|lpm_mult:Mult0 ;
;     -- LPM_WIDTHA                     ; 18                              ;
;     -- LPM_WIDTHB                     ; 17                              ;
;     -- LPM_WIDTHP                     ; 35                              ;
;     -- LPM_REPRESENTATION             ; SIGNED                          ;
;     -- INPUT_A_IS_CONSTANT            ; NO                              ;
;     -- INPUT_B_IS_CONSTANT            ; NO                              ;
;     -- USE_EAB                        ; OFF                             ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                            ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                              ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                              ;
+---------------------------------------+---------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SignalTap II Logic Analyzer Settings                                                                                                                                                                                                                        ;
+----------------+------------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+--------------------------+----------------------------+-------------------------+
; Instance Index ; Instance Name    ; Trigger Input Width ; Data Input Width ; Sample Depth ; Trigger Levels ; Advanced Trigger Levels ; Trigger In Used ; Trigger Out Used ; Power-Up Trigger Enabled ; Incremental Trigger Inputs ; Incremental Data Inputs ;
+----------------+------------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+--------------------------+----------------------------+-------------------------+
; 0              ; auto_signaltap_0 ; 4                   ; 4                ; 128          ; 1              ; 0                       ; no              ; no               ; no                       ; 0                          ; 0                       ;
+----------------+------------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+--------------------------+----------------------------+-------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition
    Info: Processing started: Tue Nov 07 15:49:08 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_Default -c DE2_Default
Info: Found 3 design units, including 3 entities, in source file DE2_Default.v
    Info: Found entity 1: DE2_Default
    Info: Found entity 2: signed_mult
    Info: Found entity 3: sync_rom
Warning: Can't analyze file -- file C:/DE2/AnalogSim/VGA_Controller/Img_RAM.v is missing
Warning: Can't analyze file -- file C:/DE2/AnalogSim/VGA_Controller/VGA_Controller.v is missing
Warning: Can't analyze file -- file C:/DE2/AnalogSim/VGA_Controller/VGA_OSD_RAM.v is missing
Warning: Can't analyze file -- file C:/DE2/AnalogSim/VGA_Controller/VGA_PLL.v is missing
Info: Found 1 design units, including 1 entities, in source file AUDIO_DAC.v
    Info: Found entity 1: AUDIO_DAC
Info: Found 1 design units, including 1 entities, in source file I2C_AV_Config.v
    Info: Found entity 1: I2C_AV_Config
Info: Found 1 design units, including 1 entities, in source file I2C_Controller.v
    Info: Found entity 1: I2C_Controller
Warning: Can't analyze file -- file C:/DE2/AnalogSim/LCD_Controller.v is missing
Warning: Can't analyze file -- file C:/DE2/AnalogSim/LCD_TEST.v is missing
Info: Found 1 design units, including 1 entities, in source file Reset_Delay.v
    Info: Found entity 1: Reset_Delay
Warning: Can't analyze file -- file C:/DE2/AnalogSim/SEG7_LUT.v is missing
Warning: Can't analyze file -- file C:/DE2/AnalogSim/SEG7_LUT_8.v is missing
Info: Found 1 design units, including 1 entities, in source file VGA_Audio_PLL.v
    Info: Found entity 1: VGA_Audio_PLL
Info: Found 1 design units, including 1 entities, in source file AUDIO_DAC_ADC.v
    Info: Found entity 1: AUDIO_DAC_ADC
Info: Elaborating entity "DE2_Default" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at DE2_Default.v(326): object "onehalf" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at DE2_Default.v(367): truncated value with size 32 to match size of target (5)
Warning (10034): Output port "HEX0[6]" at DE2_Default.v(186) has no driver
Warning (10034): Output port "HEX0[5]" at DE2_Default.v(186) has no driver
Warning (10034): Output port "HEX0[4]" at DE2_Default.v(186) has no driver
Warning (10034): Output port "HEX0[3]" at DE2_Default.v(186) has no driver
Warning (10034): Output port "HEX0[2]" at DE2_Default.v(186) has no driver
Warning (10034): Output port "HEX0[1]" at DE2_Default.v(186) has no driver
Warning (10034): Output port "HEX0[0]" at DE2_Default.v(186) has no driver
Warning (10034): Output port "HEX1[6]" at DE2_Default.v(187) has no driver
Warning (10034): Output port "HEX1[5]" at DE2_Default.v(187) has no driver
Warning (10034): Output port "HEX1[4]" at DE2_Default.v(187) has no driver
Warning (10034): Output port "HEX1[3]" at DE2_Default.v(187) has no driver
Warning (10034): Output port "HEX1[2]" at DE2_Default.v(187) has no driver
Warning (10034): Output port "HEX1[1]" at DE2_Default.v(187) has no driver
Warning (10034): Output port "HEX1[0]" at DE2_Default.v(187) has no driver
Warning (10034): Output port "HEX2[6]" at DE2_Default.v(188) has no driver
Warning (10034): Output port "HEX2[5]" at DE2_Default.v(188) has no driver
Warning (10034): Output port "HEX2[4]" at DE2_Default.v(188) has no driver
Warning (10034): Output port "HEX2[3]" at DE2_Default.v(188) has no driver
Warning (10034): Output port "HEX2[2]" at DE2_Default.v(188) has no driver
Warning (10034): Output port "HEX2[1]" at DE2_Default.v(188) has no driver
Warning (10034): Output port "HEX2[0]" at DE2_Default.v(188) has no driver
Warning (10034): Output port "HEX3[6]" at DE2_Default.v(189) has no driver
Warning (10034): Output port "HEX3[5]" at DE2_Default.v(189) has no driver
Warning (10034): Output port "HEX3[4]" at DE2_Default.v(189) has no driver
Warning (10034): Output port "HEX3[3]" at DE2_Default.v(189) has no driver
Warning (10034): Output port "HEX3[2]" at DE2_Default.v(189) has no driver
Warning (10034): Output port "HEX3[1]" at DE2_Default.v(189) has no driver
Warning (10034): Output port "HEX3[0]" at DE2_Default.v(189) has no driver
Warning (10034): Output port "HEX4[6]" at DE2_Default.v(190) has no driver
Warning (10034): Output port "HEX4[5]" at DE2_Default.v(190) has no driver
Warning (10034): Output port "HEX4[4]" at DE2_Default.v(190) has no driver
Warning (10034): Output port "HEX4[3]" at DE2_Default.v(190) has no driver
Warning (10034): Output port "HEX4[2]" at DE2_Default.v(190) has no driver
Warning (10034): Output port "HEX4[1]" at DE2_Default.v(190) has no driver
Warning (10034): Output port "HEX4[0]" at DE2_Default.v(190) has no driver
Warning (10034): Output port "HEX5[6]" at DE2_Default.v(191) has no driver
Warning (10034): Output port "HEX5[5]" at DE2_Default.v(191) has no driver
Warning (10034): Output port "HEX5[4]" at DE2_Default.v(191) has no driver
Warning (10034): Output port "HEX5[3]" at DE2_Default.v(191) has no driver
Warning (10034): Output port "HEX5[2]" at DE2_Default.v(191) has no driver
Warning (10034): Output port "HEX5[1]" at DE2_Default.v(191) has no driver
Warning (10034): Output port "HEX5[0]" at DE2_Default.v(191) has no driver
Warning (10034): Output port "HEX6[6]" at DE2_Default.v(192) has no driver
Warning (10034): Output port "HEX6[5]" at DE2_Default.v(192) has no driver
Warning (10034): Output port "HEX6[4]" at DE2_Default.v(192) has no driver
Warning (10034): Output port "HEX6[3]" at DE2_Default.v(192) has no driver
Warning (10034): Output port "HEX6[2]" at DE2_Default.v(192) has no driver
Warning (10034): Output port "HEX6[1]" at DE2_Default.v(192) has no driver
Warning (10034): Output port "HEX6[0]" at DE2_Default.v(192) has no driver
Warning (10034): Output port "HEX7[6]" at DE2_Default.v(193) has no driver
Warning (10034): Output port "HEX7[5]" at DE2_Default.v(193) has no driver
Warning (10034): Output port "HEX7[4]" at DE2_Default.v(193) has no driver
Warning (10034): Output port "HEX7[3]" at DE2_Default.v(193) has no driver
Warning (10034): Output port "HEX7[2]" at DE2_Default.v(193) has no driver
Warning (10034): Output port "HEX7[1]" at DE2_Default.v(193) has no driver
Warning (10034): Output port "HEX7[0]" at DE2_Default.v(193) has no driver
Warning (10034): Output port "LEDG[8]" at DE2_Default.v(195) has no driver
Warning (10034): Output port "LEDG[7]" at DE2_Default.v(195) has no driver
Warning (10034): Output port "LEDG[6]" at DE2_Default.v(195) has no driver
Warning (10034): Output port "LEDG[5]" at DE2_Default.v(195) has no driver
Warning (10034): Output port "LEDG[4]" at DE2_Default.v(195) has no driver
Warning (10034): Output port "LEDG[3]" at DE2_Default.v(195) has no driver
Warning (10034): Output port "LEDG[2]" at DE2_Default.v(195) has no driver
Warning (10034): Output port "LEDG[1]" at DE2_Default.v(195) has no driver
Warning (10034): Output port "LEDG[0]" at DE2_Default.v(195) has no driver
Warning (10034): Output port "LEDR[17]" at DE2_Default.v(196) has no driver
Warning (10034): Output port "LEDR[16]" at DE2_Default.v(196) has no driver
Warning (10034): Output port "LEDR[15]" at DE2_Default.v(196) has no driver
Warning (10034): Output port "LEDR[14]" at DE2_Default.v(196) has no driver
Warning (10034): Output port "LEDR[13]" at DE2_Default.v(196) has no driver
Warning (10034): Output port "LEDR[12]" at DE2_Default.v(196) has no driver
Warning (10034): Output port "LEDR[11]" at DE2_Default.v(196) has no driver
Warning (10034): Output port "LEDR[10]" at DE2_Default.v(196) has no driver
Warning (10034): Output port "LEDR[9]" at DE2_Default.v(196) has no driver
Warning (10034): Output port "LEDR[8]" at DE2_Default.v(196) has no driver
Warning (10034): Output port "LEDR[7]" at DE2_Default.v(196) has no driver
Warning (10034): Output port "LEDR[6]" at DE2_Default.v(196) has no driver
Warning (10034): Output port "LEDR[5]" at DE2_Default.v(196) has no driver
Warning (10034): Output port "LEDR[4]" at DE2_Default.v(196) has no driver
Warning (10034): Output port "LEDR[3]" at DE2_Default.v(196) has no driver
Warning (10034): Output port "LEDR[2]" at DE2_Default.v(196) has no driver
Warning (10034): Output port "LEDR[1]" at DE2_Default.v(196) has no driver
Warning (10034): Output port "LEDR[0]" at DE2_Default.v(196) has no driver
Warning (10034): Output port "UART_TXD" at DE2_Default.v(198) has no driver
Warning (10034): Output port "IRDA_TXD" at DE2_Default.v(201) has no driver
Warning (10034): Output port "DRAM_ADDR[11]" at DE2_Default.v(205) has no driver
Warning (10034): Output port "DRAM_ADDR[10]" at DE2_Default.v(205) has no driver
Warning (10034): Output port "DRAM_ADDR[9]" at DE2_Default.v(205) has no driver
Warning (10034): Output port "DRAM_ADDR[8]" at DE2_Default.v(205) has no driver
Warning (10034): Output port "DRAM_ADDR[7]" at DE2_Default.v(205) has no driver
Warning (10034): Output port "DRAM_ADDR[6]" at DE2_Default.v(205) has no driver
Warning (10034): Output port "DRAM_ADDR[5]" at DE2_Default.v(205) has no driver
Warning (10034): Output port "DRAM_ADDR[4]" at DE2_Default.v(205) has no driver
Warning (10034): Output port "DRAM_ADDR[3]" at DE2_Default.v(205) has no driver
Warning (10034): Output port "DRAM_ADDR[2]" at DE2_Default.v(205) has no driver
Warning (10034): Output port "DRAM_ADDR[1]" at DE2_Default.v(205) has no driver
Warning (10034): Output port "DRAM_ADDR[0]" at DE2_Default.v(205) has no driver
Warning (10034): Output port "DRAM_LDQM" at DE2_Default.v(206) has no driver
Warning (10034): Output port "DRAM_UDQM" at DE2_Default.v(207) has no driver
Warning (10034): Output port "DRAM_WE_N" at DE2_Default.v(208) has no driver
Warning (10034): Output port "DRAM_CAS_N" at DE2_Default.v(209) has no driver
Warning (10034): Output port "DRAM_RAS_N" at DE2_Default.v(210) has no driver
Warning (10034): Output port "DRAM_CS_N" at DE2_Default.v(211) has no driver
Warning (10034): Output port "DRAM_BA_0" at DE2_Default.v(212) has no driver
Warning (10034): Output port "DRAM_BA_1" at DE2_Default.v(213) has no driver
Warning (10034): Output port "DRAM_CLK" at DE2_Default.v(214) has no driver
Warning (10034): Output port "DRAM_CKE" at DE2_Default.v(215) has no driver
Warning (10034): Output port "FL_ADDR[21]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[20]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[19]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[18]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[17]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[16]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[15]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[14]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[13]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[12]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[11]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[10]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[9]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[8]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[7]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[6]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[5]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[4]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[3]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[2]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[1]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_ADDR[0]" at DE2_Default.v(218) has no driver
Warning (10034): Output port "FL_WE_N" at DE2_Default.v(219) has no driver
Warning (10034): Output port "FL_RST_N" at DE2_Default.v(220) has no driver
Warning (10034): Output port "FL_OE_N" at DE2_Default.v(221) has no driver
Warning (10034): Output port "FL_CE_N" at DE2_Default.v(222) has no driver
Warning (10034): Output port "SRAM_ADDR[17]" at DE2_Default.v(225) has no driver
Warning (10034): Output port "SRAM_ADDR[16]" at DE2_Default.v(225) has no driver
Warning (10034): Output port "SRAM_ADDR[15]" at DE2_Default.v(225) has no driver
Warning (10034): Output port "SRAM_ADDR[14]" at DE2_Default.v(225) has no driver
Warning (10034): Output port "SRAM_ADDR[13]" at DE2_Default.v(225) has no driver
Warning (10034): Output port "SRAM_ADDR[12]" at DE2_Default.v(225) has no driver
Warning (10034): Output port "SRAM_ADDR[11]" at DE2_Default.v(225) has no driver
Warning (10034): Output port "SRAM_ADDR[10]" at DE2_Default.v(225) has no driver
Warning (10034): Output port "SRAM_ADDR[9]" at DE2_Default.v(225) has no driver
Warning (10034): Output port "SRAM_ADDR[8]" at DE2_Default.v(225) has no driver
Warning (10034): Output port "SRAM_ADDR[7]" at DE2_Default.v(225) has no driver
Warning (10034): Output port "SRAM_ADDR[6]" at DE2_Default.v(225) has no driver
Warning (10034): Output port "SRAM_ADDR[5]" at DE2_Default.v(225) has no driver
Warning (10034): Output port "SRAM_ADDR[4]" at DE2_Default.v(225) has no driver
Warning (10034): Output port "SRAM_ADDR[3]" at DE2_Default.v(225) has no driver
Warning (10034): Output port "SRAM_ADDR[2]" at DE2_Default.v(225) has no driver
Warning (10034): Output port "SRAM_ADDR[1]" at DE2_Default.v(225) has no driver
Warning (10034): Output port "SRAM_ADDR[0]" at DE2_Default.v(225) has no driver
Warning (10034): Output port "SRAM_UB_N" at DE2_Default.v(226) has no driver
Warning (10034): Output port "SRAM_LB_N" at DE2_Default.v(227) has no driver
Warning (10034): Output port "SRAM_WE_N" at DE2_Default.v(228) has no driver
Warning (10034): Output port "SRAM_CE_N" at DE2_Default.v(229) has no driver
Warning (10034): Output port "SRAM_OE_N" at DE2_Default.v(230) has no driver
Warning (10034): Output port "OTG_ADDR[1]" at DE2_Default.v(233) has no driver
Warning (10034): Output port "OTG_ADDR[0]" at DE2_Default.v(233) has no driver
Warning (10034): Output port "OTG_CS_N" at DE2_Default.v(234) has no driver
Warning (10034): Output port "OTG_RD_N" at DE2_Default.v(235) has no driver
Warning (10034): Output port "OTG_WR_N" at DE2_Default.v(236) has no driver
Warning (10034): Output port "OTG_RST_N" at DE2_Default.v(237) has no driver
Warning (10034): Output port "OTG_FSPEED" at DE2_Default.v(238) has no driver
Warning (10034): Output port "OTG_LSPEED" at DE2_Default.v(239) has no driver
Warning (10034): Output port "OTG_DACK0_N" at DE2_Default.v(244) has no driver
Warning (10034): Output port "OTG_DACK1_N" at DE2_Default.v(245) has no driver
Warning (10034): Output port "LCD_RW" at DE2_Default.v(250) has no driver
Warning (10034): Output port "LCD_EN" at DE2_Default.v(251) has no driver
Warning (10034): Output port "LCD_RS" at DE2_Default.v(252) has no driver
Warning (10034): Output port "SD_CLK" at DE2_Default.v(257) has no driver
Warning (10034): Output port "TDO" at DE2_Default.v(268) has no driver
Warning (10034): Output port "VGA_HS" at DE2_Default.v(271) has no driver
Warning (10034): Output port "VGA_VS" at DE2_Default.v(272) has no driver
Warning (10034): Output port "VGA_BLANK" at DE2_Default.v(273) has no driver
Warning (10034): Output port "VGA_SYNC" at DE2_Default.v(274) has no driver
Warning (10034): Output port "VGA_R[9]" at DE2_Default.v(275) has no driver
Warning (10034): Output port "VGA_R[8]" at DE2_Default.v(275) has no driver
Warning (10034): Output port "VGA_R[7]" at DE2_Default.v(275) has no driver
Warning (10034): Output port "VGA_R[6]" at DE2_Default.v(275) has no driver
Warning (10034): Output port "VGA_R[5]" at DE2_Default.v(275) has no driver
Warning (10034): Output port "VGA_R[4]" at DE2_Default.v(275) has no driver
Warning (10034): Output port "VGA_R[3]" at DE2_Default.v(275) has no driver
Warning (10034): Output port "VGA_R[2]" at DE2_Default.v(275) has no driver
Warning (10034): Output port "VGA_R[1]" at DE2_Default.v(275) has no driver
Warning (10034): Output port "VGA_R[0]" at DE2_Default.v(275) has no driver
Warning (10034): Output port "VGA_G[9]" at DE2_Default.v(276) has no driver
Warning (10034): Output port "VGA_G[8]" at DE2_Default.v(276) has no driver
Warning (10034): Output port "VGA_G[7]" at DE2_Default.v(276) has no driver
Warning (10034): Output port "VGA_G[6]" at DE2_Default.v(276) has no driver
Warning (10034): Output port "VGA_G[5]" at DE2_Default.v(276) has no driver
Warning (10034): Output port "VGA_G[4]" at DE2_Default.v(276) has no driver
Warning (10034): Output port "VGA_G[3]" at DE2_Default.v(276) has no driver
Warning (10034): Output port "VGA_G[2]" at DE2_Default.v(276) has no driver
Warning (10034): Output port "VGA_G[1]" at DE2_Default.v(276) has no driver
Warning (10034): Output port "VGA_G[0]" at DE2_Default.v(276) has no driver
Warning (10034): Output port "VGA_B[9]" at DE2_Default.v(277) has no driver
Warning (10034): Output port "VGA_B[8]" at DE2_Default.v(277) has no driver
Warning (10034): Output port "VGA_B[7]" at DE2_Default.v(277) has no driver
Warning (10034): Output port "VGA_B[6]" at DE2_Default.v(277) has no driver
Warning (10034): Output port "VGA_B[5]" at DE2_Default.v(277) has no driver
Warning (10034): Output port "VGA_B[4]" at DE2_Default.v(277) has no driver
Warning (10034): Output port "VGA_B[3]" at DE2_Default.v(277) has no driver
Warning (10034): Output port "VGA_B[2]" at DE2_Default.v(277) has no driver
Warning (10034): Output port "VGA_B[1]" at DE2_Default.v(277) has no driver
Warning (10034): Output port "VGA_B[0]" at DE2_Default.v(277) has no driver
Warning (10034): Output port "ENET_CMD" at DE2_Default.v(280) has no driver
Warning (10034): Output port "ENET_CS_N" at DE2_Default.v(281) has no driver
Warning (10034): Output port "ENET_WR_N" at DE2_Default.v(282) has no driver
Warning (10034): Output port "ENET_RD_N" at DE2_Default.v(283) has no driver
Warning (10034): Output port "ENET_RST_N" at DE2_Default.v(284) has no driver
Warning (10034): Output port "ENET_CLK" at DE2_Default.v(286) has no driver
Info: Elaborating entity "Reset_Delay" for hierarchy "Reset_Delay:r0"
Warning (10230): Verilog HDL assignment warning at Reset_Delay.v(10): truncated value with size 32 to match size of target (20)
Info: Elaborating entity "VGA_Audio_PLL" for hierarchy "VGA_Audio_PLL:p1"
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "VGA_Audio_PLL:p1|altpll:altpll_component"
Info: Elaborated megafunction instantiation "VGA_Audio_PLL:p1|altpll:altpll_component"
Info: Elaborating entity "I2C_AV_Config" for hierarchy "I2C_AV_Config:u3"
Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(55): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(106): truncated value with size 32 to match size of target (6)
Info: Elaborating entity "I2C_Controller" for hierarchy "I2C_AV_Config:u3|I2C_Controller:u0"
Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(90): truncated value with size 32 to match size of target (6)
Info: Elaborating entity "AUDIO_DAC_ADC" for hierarchy "AUDIO_DAC_ADC:u4"
Warning (10036): Verilog HDL or VHDL warning at AUDIO_DAC_ADC.v(23): object "SIN_SAMPLE_DATA" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at AUDIO_DAC_ADC.v(37): object "ADC_loop" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at AUDIO_DAC_ADC.v(38): object "FLASH_DATA" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at AUDIO_DAC_ADC.v(39): object "SDRAM_DATA" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at AUDIO_DAC_ADC.v(40): object "SRAM_DATA" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at AUDIO_DAC_ADC.v(73): object "FLASH_Out" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at AUDIO_DAC_ADC.v(74): object "SDRAM_Out" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at AUDIO_DAC_ADC.v(75): object "SRAM_Out" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC_ADC.v(101): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC_ADC.v(128): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC_ADC.v(136): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC_ADC.v(144): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC_ADC.v(159): truncated value with size 32 to match size of target (20)
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC_ADC.v(195): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC_ADC.v(226): truncated value with size 32 to match size of target (18)
Warning (10230): Verilog HDL assignment warning at AUDIO_DAC_ADC.v(260): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "signed_mult" for hierarchy "signed_mult:v_12"
Warning: Port "iSrc_Select" on the entity instantiation of "u4" is connected to a signal of width 1. The formal width of the signal in the module is 2.  Extra bits will be driven by GND.
Info: Found 3 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/sld_signaltap.vhd
    Info: Found design unit 1: sld_signaltap_pack
    Info: Found design unit 2: sld_signaltap-rtl
    Info: Found entity 1: sld_signaltap
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Found 14 design units, including 7 entities, in source file ../../altera/quartus60/libraries/megafunctions/sld_ela_control.vhd
    Info: Found design unit 1: sld_ela_control-rtl
    Info: Found design unit 2: sld_ela_level_seq_mgr-rtl
    Info: Found design unit 3: sld_ela_state_machine-rtl
    Info: Found design unit 4: sld_ela_seg_state_machine-rtl
    Info: Found design unit 5: sld_ela_post_trigger_counter-rtl
    Info: Found design unit 6: sld_ela_segment_mgr-rtl
    Info: Found design unit 7: sld_ela_basic_multi_level_trigger-rtl
    Info: Found entity 1: sld_ela_control
    Info: Found entity 2: sld_ela_level_seq_mgr
    Info: Found entity 3: sld_ela_state_machine
    Info: Found entity 4: sld_ela_seg_state_machine
    Info: Found entity 5: sld_ela_post_trigger_counter
    Info: Found entity 6: sld_ela_segment_mgr
    Info: Found entity 7: sld_ela_basic_multi_level_trigger
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf
    Info: Found entity 1: lpm_shiftreg
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Found 4 design units, including 2 entities, in source file ../../altera/quartus60/libraries/megafunctions/sld_mbpmg.vhd
    Info: Found design unit 1: sld_mbpmg-rtl
    Info: Found design unit 2: sld_sbpmg-rtl
    Info: Found entity 1: sld_mbpmg
    Info: Found entity 2: sld_sbpmg
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_state_machine:sm1", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_post_trigger_counter:\gen_non_zero_sample_depth:tc1", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_post_trigger_counter:\gen_non_zero_sample_depth:tc1|lpm_counter:post_trigger_counter", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Found 1 design units, including 1 entities, in source file db/cntr_mhg.tdf
    Info: Found entity 1: cntr_mhg
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Found 1 design units, including 1 entities, in source file db/cntr_lqf.tdf
    Info: Found entity 1: cntr_lqf
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/lpm_compare.tdf
    Info: Found entity 1: lpm_compare
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Found 1 design units, including 1 entities, in source file db/cmpr_nth.tdf
    Info: Found entity 1: cmpr_nth
Info: Found 4 design units, including 2 entities, in source file ../../altera/quartus60/libraries/megafunctions/sld_acquisition_buffer.vhd
    Info: Found design unit 1: sld_acquisition_buffer-rtl
    Info: Found design unit 2: sld_offload_buffer_mgr-rtl
    Info: Found entity 1: sld_acquisition_buffer
    Info: Found entity 2: sld_offload_buffer_mgr
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Found 1 design units, including 1 entities, in source file db/cntr_blh.tdf
    Info: Found entity 1: cntr_blh
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/lpm_ff.tdf
    Info: Found entity 1: lpm_ff
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_ff:\gen_non_zero_sample_depth:trigger_address_register", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_5oi2.tdf
    Info: Found entity 1: altsyncram_5oi2
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Found 1 design units, including 1 entities, in source file db/cntr_9ne.tdf
    Info: Found entity 1: cntr_9ne
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Found 1 design units, including 1 entities, in source file db/cntr_1ff.tdf
    Info: Found entity 1: cntr_1ff
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Found 2 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd
    Info: Found design unit 1: sld_rom_sr-INFO_REG
    Info: Found entity 1: sld_rom_sr
Info: Elaborated megafunction instantiation "sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr", which is child of megafunction instantiation "sld_signaltap:auto_signaltap_0"
Info: Instantiated megafunction "sld_signaltap:auto_signaltap_0" with the following parameter:
    Info: Parameter "SLD_NODE_INFO" = "536899072"
    Info: Parameter "SLD_POWER_UP_TRIGGER" = "0"
    Info: Parameter "SLD_TRIGGER_LEVEL" = "1"
    Info: Parameter "SLD_SAMPLE_DEPTH" = "128"
    Info: Parameter "SLD_MEM_ADDRESS_BITS" = "7"
    Info: Parameter "SLD_TRIGGER_IN_ENABLED" = "0"
    Info: Parameter "SLD_ADVANCED_TRIGGER_ENTITY" = "basic,1,"
    Info: Parameter "SLD_TRIGGER_LEVEL_PIPELINE" = "1"
    Info: Parameter "SLD_ENABLE_ADVANCED_TRIGGER" = "0"
    Info: Parameter "SLD_DATA_BITS" = "4"
    Info: Parameter "SLD_TRIGGER_BITS" = "4"
    Info: Parameter "SLD_INVERSION_MASK" = "0000000000000000000000000000"
    Info: Parameter "SLD_INVERSION_MASK_LENGTH" = "28"
    Info: Parameter "SLD_NODE_CRC_LOWORD" = "33425"
    Info: Parameter "SLD_NODE_CRC_HIWORD" = "21303"
    Info: Parameter "SLD_DATA_BIT_CNTR_BITS" = "2"
Info: Analysis and Synthesis generated SignalTap II or debug node instance "auto_signaltap_0"
    Info: Source node "|DE2_Default|CLOCK_50" connects to port "acq_clk"
    Info: Source node "|DE2_Default|KEY[0]" connects to port "acq_trigger_in[0]"
    Info: Source node "|DE2_Default|KEY[0]" connects to port "acq_data_in[0]"
    Info: Source node "|DE2_Default|KEY[1]" connects to port "acq_trigger_in[1]"
    Info: Source node "|DE2_Default|KEY[1]" connects to port "acq_data_in[1]"
    Info: Source node "|DE2_Default|KEY[2]" connects to port "acq_trigger_in[2]"
    Info: Source node "|DE2_Default|KEY[2]" connects to port "acq_data_in[2]"
    Info: Source node "|DE2_Default|KEY[3]" connects to port "acq_trigger_in[3]"
    Info: Source node "|DE2_Default|KEY[3]" connects to port "acq_data_in[3]"
Info: Found 6 design units, including 2 entities, in source file ../../altera/quartus60/libraries/megafunctions/sld_hub.vhd
    Info: Found design unit 1: HUB_PACK
    Info: Found design unit 2: JTAG_PACK
    Info: Found design unit 3: sld_hub-rtl
    Info: Found design unit 4: sld_jtag_state_machine-rtl
    Info: Found entity 1: sld_hub
    Info: Found entity 2: sld_jtag_state_machine
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst"
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "1"
    Info: Parameter "N_SEL_BITS" = "1"
    Info: Parameter "N_NODE_IR_BITS" = "8"
    Info: Parameter "NODE_INFO" = "00100000000000000110111000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "1"
    Info: Parameter "N_SEL_BITS" = "1"
    Info: Parameter "N_NODE_IR_BITS" = "8"
    Info: Parameter "NODE_INFO" = "00100000000000000110111000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/lpm_decode.tdf
    Info: Found entity 1: lpm_decode
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|lpm_decode:instruction_decoder", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "1"
    Info: Parameter "N_SEL_BITS" = "1"
    Info: Parameter "N_NODE_IR_BITS" = "8"
    Info: Parameter "NODE_INFO" = "00100000000000000110111000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Found 1 design units, including 1 entities, in source file db/decode_aoi.tdf
    Info: Found entity 1: decode_aoi
Info: Found 2 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/sld_dffex.vhd
    Info: Found design unit 1: sld_dffex-DFFEX
    Info: Found entity 1: sld_dffex
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:RESET", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "1"
    Info: Parameter "N_SEL_BITS" = "1"
    Info: Parameter "N_NODE_IR_BITS" = "8"
    Info: Parameter "NODE_INFO" = "00100000000000000110111000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:IRSR", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "1"
    Info: Parameter "N_SEL_BITS" = "1"
    Info: Parameter "N_NODE_IR_BITS" = "8"
    Info: Parameter "NODE_INFO" = "00100000000000000110111000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "1"
    Info: Parameter "N_SEL_BITS" = "1"
    Info: Parameter "N_NODE_IR_BITS" = "8"
    Info: Parameter "NODE_INFO" = "00100000000000000110111000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "1"
    Info: Parameter "N_SEL_BITS" = "1"
    Info: Parameter "N_NODE_IR_BITS" = "8"
    Info: Parameter "NODE_INFO" = "00100000000000000110111000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Warning: Reduced register "I2C_AV_Config:u3|mI2C_DATA[23]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u3|mI2C_DATA[19]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u3|mI2C_DATA[17]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u3|mI2C_DATA[16]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u3|mI2C_DATA[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u3|mI2C_DATA[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u3|mI2C_DATA[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u3|mI2C_DATA[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u3|mI2C_DATA[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u3|I2C_Controller:u0|SD[23]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u3|I2C_Controller:u0|SD[19]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u3|I2C_Controller:u0|SD[17]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u3|I2C_Controller:u0|SD[16]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u3|I2C_Controller:u0|SD[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u3|I2C_Controller:u0|SD[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u3|I2C_Controller:u0|SD[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u3|I2C_Controller:u0|SD[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u3|I2C_Controller:u0|SD[7]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "I2C_AV_Config:u3|mI2C_DATA[21]" merged to single register "I2C_AV_Config:u3|mI2C_DATA[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u3|mI2C_DATA[20]" merged to single register "I2C_AV_Config:u3|mI2C_DATA[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u3|mI2C_DATA[18]" merged to single register "I2C_AV_Config:u3|mI2C_DATA[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u3|mI2C_DATA[5]" merged to single register "I2C_AV_Config:u3|mI2C_DATA[6]"
    Info: Duplicate register "I2C_AV_Config:u3|I2C_Controller:u0|SD[21]" merged to single register "I2C_AV_Config:u3|I2C_Controller:u0|SD[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u3|I2C_Controller:u0|SD[20]" merged to single register "I2C_AV_Config:u3|I2C_Controller:u0|SD[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u3|I2C_Controller:u0|SD[18]" merged to single register "I2C_AV_Config:u3|I2C_Controller:u0|SD[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u3|I2C_Controller:u0|SD[5]" merged to single register "I2C_AV_Config:u3|I2C_Controller:u0|SD[6]"
Info: State machine "|DE2_Default|I2C_AV_Config:u3|mSetup_ST" contains 3 states
Info: Selected Auto state machine encoding method for state machine "|DE2_Default|I2C_AV_Config:u3|mSetup_ST"
Info: Encoding result for state machine "|DE2_Default|I2C_AV_Config:u3|mSetup_ST"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "I2C_AV_Config:u3|mSetup_ST.0000"
        Info: Encoded state bit "I2C_AV_Config:u3|mSetup_ST.0010"
        Info: Encoded state bit "I2C_AV_Config:u3|mSetup_ST.0001"
    Info: State "|DE2_Default|I2C_AV_Config:u3|mSetup_ST.0000" uses code string "000"
    Info: State "|DE2_Default|I2C_AV_Config:u3|mSetup_ST.0001" uses code string "101"
    Info: State "|DE2_Default|I2C_AV_Config:u3|mSetup_ST.0010" uses code string "110"
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus60/libraries/megafunctions/lpm_mult.tdf
    Info: Found entity 1: lpm_mult
Info: Elaborated megafunction instantiation "signed_mult:v_22|lpm_mult:Mult0"
Info: Found 1 design units, including 1 entities, in source file db/mult_co01.tdf
    Info: Found entity 1: mult_co01
Warning: The bidir "LCD_DATA[0]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[1]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[2]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[3]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[4]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[5]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[6]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[7]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SD_DAT3" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SD_CMD" has no source; inserted an always disabled tri-state buffer.
Info: Duplicate registers merged to single register
    Info: Duplicate register "sld_signaltap:auto_signaltap_0|acq_data_in_reg[3]" merged to single register "sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[3]"
    Info: Duplicate register "sld_signaltap:auto_signaltap_0|acq_data_in_pipe_reg[1][3]" merged to single register "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|holdff"
    Info: Duplicate register "sld_signaltap:auto_signaltap_0|acq_data_in_reg[0]" merged to single register "sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[0]"
    Info: Duplicate register "sld_signaltap:auto_signaltap_0|acq_data_in_pipe_reg[1][0]" merged to single register "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|holdff"
    Info: Duplicate register "sld_signaltap:auto_signaltap_0|acq_data_in_reg[2]" merged to single register "sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[2]"
    Info: Duplicate register "sld_signaltap:auto_signaltap_0|acq_data_in_pipe_reg[1][2]" merged to single register "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|holdff"
    Info: Duplicate register "sld_signaltap:auto_signaltap_0|acq_data_in_reg[1]" merged to single register "sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[1]"
    Info: Duplicate register "sld_signaltap:auto_signaltap_0|acq_data_in_pipe_reg[1][1]" merged to single register "sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|holdff"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: Reduced register "AUDIO_DAC_ADC:u4|BCK_DIV[3]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "HEX0[0]" stuck at GND
    Warning: Pin "HEX0[1]" stuck at GND
    Warning: Pin "HEX0[2]" stuck at GND
    Warning: Pin "HEX0[3]" stuck at GND
    Warning: Pin "HEX0[4]" stuck at GND
    Warning: Pin "HEX0[5]" stuck at GND
    Warning: Pin "HEX0[6]" stuck at GND
    Warning: Pin "HEX1[0]" stuck at GND
    Warning: Pin "HEX1[1]" stuck at GND
    Warning: Pin "HEX1[2]" stuck at GND
    Warning: Pin "HEX1[3]" stuck at GND
    Warning: Pin "HEX1[4]" stuck at GND
    Warning: Pin "HEX1[5]" stuck at GND
    Warning: Pin "HEX1[6]" stuck at GND
    Warning: Pin "HEX2[0]" stuck at GND
    Warning: Pin "HEX2[1]" stuck at GND
    Warning: Pin "HEX2[2]" stuck at GND
    Warning: Pin "HEX2[3]" stuck at GND
    Warning: Pin "HEX2[4]" stuck at GND
    Warning: Pin "HEX2[5]" stuck at GND
    Warning: Pin "HEX2[6]" stuck at GND
    Warning: Pin "HEX3[0]" stuck at GND
    Warning: Pin "HEX3[1]" stuck at GND
    Warning: Pin "HEX3[2]" stuck at GND
    Warning: Pin "HEX3[3]" stuck at GND
    Warning: Pin "HEX3[4]" stuck at GND
    Warning: Pin "HEX3[5]" stuck at GND
    Warning: Pin "HEX3[6]" stuck at GND
    Warning: Pin "HEX4[0]" stuck at GND
    Warning: Pin "HEX4[1]" stuck at GND
    Warning: Pin "HEX4[2]" stuck at GND
    Warning: Pin "HEX4[3]" stuck at GND
    Warning: Pin "HEX4[4]" stuck at GND
    Warning: Pin "HEX4[5]" stuck at GND
    Warning: Pin "HEX4[6]" stuck at GND
    Warning: Pin "HEX5[0]" stuck at GND
    Warning: Pin "HEX5[1]" stuck at GND
    Warning: Pin "HEX5[2]" stuck at GND
    Warning: Pin "HEX5[3]" stuck at GND
    Warning: Pin "HEX5[4]" stuck at GND
    Warning: Pin "HEX5[5]" stuck at GND
    Warning: Pin "HEX5[6]" stuck at GND
    Warning: Pin "HEX6[0]" stuck at GND
    Warning: Pin "HEX6[1]" stuck at GND
    Warning: Pin "HEX6[2]" stuck at GND
    Warning: Pin "HEX6[3]" stuck at GND
    Warning: Pin "HEX6[4]" stuck at GND
    Warning: Pin "HEX6[5]" stuck at GND
    Warning: Pin "HEX6[6]" stuck at GND
    Warning: Pin "HEX7[0]" stuck at GND
    Warning: Pin "HEX7[1]" stuck at GND
    Warning: Pin "HEX7[2]" stuck at GND
    Warning: Pin "HEX7[3]" stuck at GND
    Warning: Pin "HEX7[4]" stuck at GND
    Warning: Pin "HEX7[5]" stuck at GND
    Warning: Pin "HEX7[6]" stuck at GND
    Warning: Pin "LEDG[0]" stuck at GND
    Warning: Pin "LEDG[1]" stuck at GND
    Warning: Pin "LEDG[2]" stuck at GND
    Warning: Pin "LEDG[3]" stuck at GND
    Warning: Pin "LEDG[4]" stuck at GND
    Warning: Pin "LEDG[5]" stuck at GND
    Warning: Pin "LEDG[6]" stuck at GND
    Warning: Pin "LEDG[7]" stuck at GND
    Warning: Pin "LEDG[8]" stuck at GND
    Warning: Pin "LEDR[0]" stuck at GND
    Warning: Pin "LEDR[1]" stuck at GND
    Warning: Pin "LEDR[2]" stuck at GND
    Warning: Pin "LEDR[3]" stuck at GND
    Warning: Pin "LEDR[4]" stuck at GND
    Warning: Pin "LEDR[5]" stuck at GND
    Warning: Pin "LEDR[6]" stuck at GND
    Warning: Pin "LEDR[7]" stuck at GND
    Warning: Pin "LEDR[8]" stuck at GND
    Warning: Pin "LEDR[9]" stuck at GND
    Warning: Pin "LEDR[10]" stuck at GND
    Warning: Pin "LEDR[11]" stuck at GND
    Warning: Pin "LEDR[12]" stuck at GND
    Warning: Pin "LEDR[13]" stuck at GND
    Warning: Pin "LEDR[14]" stuck at GND
    Warning: Pin "LEDR[15]" stuck at GND
    Warning: Pin "LEDR[16]" stuck at GND
    Warning: Pin "LEDR[17]" stuck at GND
    Warning: Pin "UART_TXD" stuck at GND
    Warning: Pin "IRDA_TXD" stuck at GND
    Warning: Pin "DRAM_ADDR[0]" stuck at GND
    Warning: Pin "DRAM_ADDR[1]" stuck at GND
    Warning: Pin "DRAM_ADDR[2]" stuck at GND
    Warning: Pin "DRAM_ADDR[3]" stuck at GND
    Warning: Pin "DRAM_ADDR[4]" stuck at GND
    Warning: Pin "DRAM_ADDR[5]" stuck at GND
    Warning: Pin "DRAM_ADDR[6]" stuck at GND
    Warning: Pin "DRAM_ADDR[7]" stuck at GND
    Warning: Pin "DRAM_ADDR[8]" stuck at GND
    Warning: Pin "DRAM_ADDR[9]" stuck at GND
    Warning: Pin "DRAM_ADDR[10]" stuck at GND
    Warning: Pin "DRAM_ADDR[11]" stuck at GND
    Warning: Pin "DRAM_LDQM" stuck at GND
    Warning: Pin "DRAM_UDQM" stuck at GND
    Warning: Pin "DRAM_WE_N" stuck at GND
    Warning: Pin "DRAM_CAS_N" stuck at GND
    Warning: Pin "DRAM_RAS_N" stuck at GND
    Warning: Pin "DRAM_CS_N" stuck at GND
    Warning: Pin "DRAM_BA_0" stuck at GND
    Warning: Pin "DRAM_BA_1" stuck at GND
    Warning: Pin "DRAM_CLK" stuck at GND
    Warning: Pin "DRAM_CKE" stuck at GND
    Warning: Pin "FL_ADDR[0]" stuck at GND
    Warning: Pin "FL_ADDR[1]" stuck at GND
    Warning: Pin "FL_ADDR[2]" stuck at GND
    Warning: Pin "FL_ADDR[3]" stuck at GND
    Warning: Pin "FL_ADDR[4]" stuck at GND
    Warning: Pin "FL_ADDR[5]" stuck at GND
    Warning: Pin "FL_ADDR[6]" stuck at GND
    Warning: Pin "FL_ADDR[7]" stuck at GND
    Warning: Pin "FL_ADDR[8]" stuck at GND
    Warning: Pin "FL_ADDR[9]" stuck at GND
    Warning: Pin "FL_ADDR[10]" stuck at GND
    Warning: Pin "FL_ADDR[11]" stuck at GND
    Warning: Pin "FL_ADDR[12]" stuck at GND
    Warning: Pin "FL_ADDR[13]" stuck at GND
    Warning: Pin "FL_ADDR[14]" stuck at GND
    Warning: Pin "FL_ADDR[15]" stuck at GND
    Warning: Pin "FL_ADDR[16]" stuck at GND
    Warning: Pin "FL_ADDR[17]" stuck at GND
    Warning: Pin "FL_ADDR[18]" stuck at GND
    Warning: Pin "FL_ADDR[19]" stuck at GND
    Warning: Pin "FL_ADDR[20]" stuck at GND
    Warning: Pin "FL_ADDR[21]" stuck at GND
    Warning: Pin "FL_WE_N" stuck at GND
    Warning: Pin "FL_RST_N" stuck at GND
    Warning: Pin "FL_OE_N" stuck at GND
    Warning: Pin "FL_CE_N" stuck at GND
    Warning: Pin "SRAM_ADDR[0]" stuck at GND
    Warning: Pin "SRAM_ADDR[1]" stuck at GND
    Warning: Pin "SRAM_ADDR[2]" stuck at GND
    Warning: Pin "SRAM_ADDR[3]" stuck at GND
    Warning: Pin "SRAM_ADDR[4]" stuck at GND
    Warning: Pin "SRAM_ADDR[5]" stuck at GND
    Warning: Pin "SRAM_ADDR[6]" stuck at GND
    Warning: Pin "SRAM_ADDR[7]" stuck at GND
    Warning: Pin "SRAM_ADDR[8]" stuck at GND
    Warning: Pin "SRAM_ADDR[9]" stuck at GND
    Warning: Pin "SRAM_ADDR[10]" stuck at GND
    Warning: Pin "SRAM_ADDR[11]" stuck at GND
    Warning: Pin "SRAM_ADDR[12]" stuck at GND
    Warning: Pin "SRAM_ADDR[13]" stuck at GND
    Warning: Pin "SRAM_ADDR[14]" stuck at GND
    Warning: Pin "SRAM_ADDR[15]" stuck at GND
    Warning: Pin "SRAM_ADDR[16]" stuck at GND
    Warning: Pin "SRAM_ADDR[17]" stuck at GND
    Warning: Pin "SRAM_UB_N" stuck at GND
    Warning: Pin "SRAM_LB_N" stuck at GND
    Warning: Pin "SRAM_WE_N" stuck at GND
    Warning: Pin "SRAM_CE_N" stuck at GND
    Warning: Pin "SRAM_OE_N" stuck at GND
    Warning: Pin "OTG_ADDR[0]" stuck at GND
    Warning: Pin "OTG_ADDR[1]" stuck at GND
    Warning: Pin "OTG_CS_N" stuck at GND
    Warning: Pin "OTG_RD_N" stuck at GND
    Warning: Pin "OTG_WR_N" stuck at GND
    Warning: Pin "OTG_RST_N" stuck at GND
    Warning: Pin "OTG_FSPEED" stuck at GND
    Warning: Pin "OTG_LSPEED" stuck at GND
    Warning: Pin "OTG_DACK0_N" stuck at GND
    Warning: Pin "OTG_DACK1_N" stuck at GND
    Warning: Pin "LCD_ON" stuck at GND
    Warning: Pin "LCD_BLON" stuck at GND
    Warning: Pin "LCD_RW" stuck at GND
    Warning: Pin "LCD_EN" stuck at GND
    Warning: Pin "LCD_RS" stuck at GND
    Warning: Pin "SD_CLK" stuck at GND
    Warning: Pin "TDO" stuck at GND
    Warning: Pin "VGA_HS" stuck at GND
    Warning: Pin "VGA_VS" stuck at GND
    Warning: Pin "VGA_BLANK" stuck at GND
    Warning: Pin "VGA_SYNC" stuck at GND
    Warning: Pin "VGA_R[0]" stuck at GND
    Warning: Pin "VGA_R[1]" stuck at GND
    Warning: Pin "VGA_R[2]" stuck at GND
    Warning: Pin "VGA_R[3]" stuck at GND
    Warning: Pin "VGA_R[4]" stuck at GND
    Warning: Pin "VGA_R[5]" stuck at GND
    Warning: Pin "VGA_R[6]" stuck at GND
    Warning: Pin "VGA_R[7]" stuck at GND
    Warning: Pin "VGA_R[8]" stuck at GND
    Warning: Pin "VGA_R[9]" stuck at GND
    Warning: Pin "VGA_G[0]" stuck at GND
    Warning: Pin "VGA_G[1]" stuck at GND
    Warning: Pin "VGA_G[2]" stuck at GND
    Warning: Pin "VGA_G[3]" stuck at GND
    Warning: Pin "VGA_G[4]" stuck at GND
    Warning: Pin "VGA_G[5]" stuck at GND
    Warning: Pin "VGA_G[6]" stuck at GND
    Warning: Pin "VGA_G[7]" stuck at GND
    Warning: Pin "VGA_G[8]" stuck at GND
    Warning: Pin "VGA_G[9]" stuck at GND
    Warning: Pin "VGA_B[0]" stuck at GND
    Warning: Pin "VGA_B[1]" stuck at GND
    Warning: Pin "VGA_B[2]" stuck at GND
    Warning: Pin "VGA_B[3]" stuck at GND
    Warning: Pin "VGA_B[4]" stuck at GND
    Warning: Pin "VGA_B[5]" stuck at GND
    Warning: Pin "VGA_B[6]" stuck at GND
    Warning: Pin "VGA_B[7]" stuck at GND
    Warning: Pin "VGA_B[8]" stuck at GND
    Warning: Pin "VGA_B[9]" stuck at GND
    Warning: Pin "ENET_CMD" stuck at GND
    Warning: Pin "ENET_CS_N" stuck at GND
    Warning: Pin "ENET_WR_N" stuck at GND
    Warning: Pin "ENET_RD_N" stuck at GND
    Warning: Pin "ENET_RST_N" stuck at GND
    Warning: Pin "ENET_CLK" stuck at GND
    Warning: Pin "TD_RESET" stuck at VCC
Warning: Design contains 24 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "EXT_CLOCK"
    Warning: No output dependent on input pin "SW[16]"
    Warning: No output dependent on input pin "UART_RXD"
    Warning: No output dependent on input pin "IRDA_RXD"
    Warning: No output dependent on input pin "OTG_INT0"
    Warning: No output dependent on input pin "OTG_INT1"
    Warning: No output dependent on input pin "OTG_DREQ0"
    Warning: No output dependent on input pin "OTG_DREQ1"
    Warning: No output dependent on input pin "TDI"
    Warning: No output dependent on input pin "TCK"
    Warning: No output dependent on input pin "TCS"
    Warning: No output dependent on input pin "PS2_DAT"
    Warning: No output dependent on input pin "PS2_CLK"
    Warning: No output dependent on input pin "ENET_INT"
    Warning: No output dependent on input pin "TD_DATA[0]"
    Warning: No output dependent on input pin "TD_DATA[1]"
    Warning: No output dependent on input pin "TD_DATA[2]"
    Warning: No output dependent on input pin "TD_DATA[3]"
    Warning: No output dependent on input pin "TD_DATA[4]"
    Warning: No output dependent on input pin "TD_DATA[5]"
    Warning: No output dependent on input pin "TD_DATA[6]"
    Warning: No output dependent on input pin "TD_DATA[7]"
    Warning: No output dependent on input pin "TD_HS"
    Warning: No output dependent on input pin "TD_VS"
Info: Implemented 1235 device resources after synthesis - the final resource count might be different
    Info: Implemented 51 input pins
    Info: Implemented 222 output pins
    Info: Implemented 156 bidirectional pins
    Info: Implemented 792 logic cells
    Info: Implemented 4 RAM segments
    Info: Implemented 1 ClockLock PLLs
    Info: Implemented 8 DSP elements
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 511 warnings
    Info: Processing ended: Tue Nov 07 15:49:25 2006
    Info: Elapsed time: 00:00:17


